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Explorer
Explorer
543 Views
Registered: ‎02-18-2013

Strange synthesis error with Vivado 2019.1

Hello,

I´ve upgraded my Vivado version to 2019.1 and build two projects, which are successfully built with 2018.2, in 2019.1 and booth projects generate this error (one project with VTC and one with XADC, but same error):

The output of the TCL console looks like this:

start_gui
open_project /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.xpr
open_project /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/daniel/Schreibtisch/Git/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/Xilinx/Vivado/2019.1/data/ip'.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'Video.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
Video_clk_wiz_0_0
Video_proc_sys_reset_0_0
Video_xbar_0
Video_axi_vdma_0_0
Video_v_tc_0_0
Video_axi_gpio_0_0
Video_v_axi4s_vid_out_0_0
Video_ps7_0_axi_periph_0
Video_auto_pc_0
Video_rst_ps7_0_50M_0
Video_axi_smc_0

INFO: [Project 1-230] Project 'Video.xpr' upgraded for this version of Vivado.
open_project: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 6541.340 ; gain = 198.523 ; free physical = 4255 ; free virtual = 9200
report_ip_status -name ip_status 
update_compile_order -fileset sources_1
upgrade_ip [get_ips  {Video_ps7_0_axi_periph_0 Video_axi_smc_0 Video_axi_vdma_0_0 Video_v_tc_0_0 Video_rst_ps7_0_50M_0 Video_axi_gpio_0_0 Video_proc_sys_reset_0_0 Video_clk_wiz_0_0 Video_v_axi4s_vid_out_0_0}] -log ip_upgrade.log
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - ProcessingSystem
Adding component instance block -- xilinx.com:ip:v_tc:6.1 - VideoTiming
Adding component instance block -- xilinx.com:ip:axi_vdma:6.3 - VideoDMA
Adding component instance block -- xilinx.com:ip:v_axi4s_vid_out:4.0 - VideoOut
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - ProcessorReset
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - AXI
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - Buttons
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - VideoReset
Adding component instance block -- www.kampis-elektroecke.de:Kampis-Elektroecke:VGA_Decimate:1.0 - VGA_Decimate
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - MainClock
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <Video> from BD file </home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/Video.bd>
Upgrading '/home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/Video.bd'
INFO: [IP_Flow 19-3422] Upgraded Video_axi_gpio_0_0 (AXI GPIO 2.0) from revision 19 to revision 21
INFO: [IP_Flow 19-3422] Upgraded Video_axi_smc_0 (AXI SmartConnect 1.0) from revision 9 to revision 11
INFO: [IP_Flow 19-3422] Upgraded Video_axi_vdma_0_0 (AXI Video Direct Memory Access 6.3) from revision 5 to revision 7
INFO: [IP_Flow 19-3422] Upgraded Video_clk_wiz_0_0 (Clocking Wizard 6.0) from revision 1 to revision 3
INFO: [IP_Flow 19-3422] Upgraded Video_proc_sys_reset_0_0 (Processor System Reset 5.0) from revision 12 to revision 13
INFO: [IP_Flow 19-3422] Upgraded Video_ps7_0_axi_periph_0 (AXI Interconnect 2.1) from revision 18 to revision 20
INFO: [IP_Flow 19-3422] Upgraded Video_rst_ps7_0_50M_0 (Processor System Reset 5.0) from revision 12 to revision 13
INFO: [IP_Flow 19-3422] Upgraded Video_v_axi4s_vid_out_0_0 (AXI4-Stream to Video Out 4.0) from revision 9 to revision 10
WARNING: [IP_Flow 19-4698] Upgrade has added port 'fifo_read_level'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'Video_v_axi4s_vid_out_0_0'. These changes may impact your design.
INFO: [IP_Flow 19-3422] Upgraded Video_v_tc_0_0 (Video Timing Controller 6.1) from revision 12 to revision 13
CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'Video_v_axi4s_vid_out_0_0' has identified issues that may require user intervention. Please review the upgrade log '/home/daniel/Schreibtisch/Git/Zybo/Examples/Video/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/Video.bd> 
INFO: [BD 41-2124] The block design file </home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/Video.bd> has changed from an XML format to a JSON format. All flows are expected to work as in prior versions of Vivado. Please contact your Xilinx Support representative, in case of any issues.
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/ui/bd_24fd3e9b.ui> 
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/daniel/Schreibtisch/Git/Zybo/Examples/Video/ip_upgrade.log'.
upgrade_ip: Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 6750.469 ; gain = 33.043 ; free physical = 4001 ; free virtual = 8987
export_ip_user_files -of_objects [get_ips {Video_ps7_0_axi_periph_0 Video_axi_smc_0 Video_axi_vdma_0_0 Video_v_tc_0_0 Video_rst_ps7_0_50M_0 Video_axi_gpio_0_0 Video_proc_sys_reset_0_0 Video_clk_wiz_0_0 Video_v_axi4s_vid_out_0_0}] -no_script -sync -force -quiet
report_ip_status -name ip_status 
regenerate_bd_layout
regenerate_bd_layout
regenerate_bd_layout
regenerate_bd_layout
regenerate_bd_layout
regenerate_bd_layout
validate_bd_design
validate_bd_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 6797.473 ; gain = 29.688 ; free physical = 3939 ; free virtual = 8927
report_ip_status -name ip_status 
save_bd_design
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/Video.bd> 
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/ui/bd_24fd3e9b.ui> 
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
INFO: [BD 41-1662] The design 'Video.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/synth/Video.v
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/sim/Video.v
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/hdl/Video_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block VideoTiming .
INFO: [BD 41-1029] Generation completed for the IP Integrator block VideoDMA .
INFO: [BD 41-1029] Generation completed for the IP Integrator block VideoOut .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ProcessorReset .
INFO: [BD 41-1029] Generation completed for the IP Integrator block VGA_Decimate .
Exporting to file /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/ip/Video_axi_smc_0/bd_0/hw_handoff/Video_axi_smc_0.hwh
Generated Block Design Tcl file /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/ip/Video_axi_smc_0/bd_0/hw_handoff/Video_axi_smc_0_bd.tcl
Generated Hardware Definition File /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/ip/Video_axi_smc_0/bd_0/synth/Video_axi_smc_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block AXI .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ProcessingSystem .
INFO: [BD 41-1029] Generation completed for the IP Integrator block Buttons .
INFO: [BD 41-1029] Generation completed for the IP Integrator block VideoReset .
INFO: [BD 41-1029] Generation completed for the IP Integrator block MainClock .
INFO: [BD 41-1029] Generation completed for the IP Integrator block AXI_Lite/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/ip/Video_auto_pc_0/Video_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block AXI_Lite/s00_couplers/auto_pc .
Exporting to file /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/hw_handoff/Video.hwh
Generated Block Design Tcl file /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/hw_handoff/Video_bd.tcl
Generated Hardware Definition File /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.srcs/sources_1/bd/Video/synth/Video.hwdef
[Sun Jun  2 20:45:48 2019] Launched Video_VGA_Decimate_0_0_synth_1, Video_axi_smc_0_synth_1, Video_ProcessingSystem_0_synth_1, Video_proc_sys_reset_0_0_synth_1, Video_clk_wiz_0_0_synth_1, Video_axi_gpio_0_0_synth_1, Video_v_tc_0_0_synth_1, Video_axi_vdma_0_0_synth_1, Video_v_axi4s_vid_out_0_0_synth_1, Video_rst_ps7_0_50M_0_synth_1, Video_xbar_0_synth_1, Video_auto_pc_0_synth_1, synth_1...
Run output will be captured here:
Video_VGA_Decimate_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_VGA_Decimate_0_0_synth_1/runme.log
Video_axi_smc_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_axi_smc_0_synth_1/runme.log
Video_ProcessingSystem_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_ProcessingSystem_0_synth_1/runme.log
Video_proc_sys_reset_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_proc_sys_reset_0_0_synth_1/runme.log
Video_clk_wiz_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_clk_wiz_0_0_synth_1/runme.log
Video_axi_gpio_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_axi_gpio_0_0_synth_1/runme.log
Video_v_tc_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_v_tc_0_0_synth_1/runme.log
Video_axi_vdma_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_axi_vdma_0_0_synth_1/runme.log
Video_v_axi4s_vid_out_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_v_axi4s_vid_out_0_0_synth_1/runme.log
Video_rst_ps7_0_50M_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_rst_ps7_0_50M_0_synth_1/runme.log
Video_xbar_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_xbar_0_synth_1/runme.log
Video_auto_pc_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/Video_auto_pc_0_synth_1/runme.log
synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/synth_1/runme.log
[Sun Jun  2 20:45:49 2019] Launched impl_1...
Run output will be captured here: /home/daniel/Schreibtisch/Git/Zybo/Examples/Video/Video.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:01:25 ; elapsed = 00:01:22 . Memory (MB): peak = 7237.770 ; gain = 420.281 ; free physical = 3620 ; free virtual = 8701
report_ip_status -name ip_status 
close_project
open_project /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.xpr
open_project /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/daniel/Schreibtisch/Git/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/Xilinx/Vivado/2019.1/data/ip'.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'XADC.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
XADC_auto_pc_0
XADC_rst_ps7_0_50M_0
XADC_xadc_wiz_0_0
XADC_ps7_0_axi_periph_0

INFO: [Project 1-230] Project 'XADC.xpr' upgraded for this version of Vivado.
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 7237.770 ; gain = 0.000 ; free physical = 3319 ; free virtual = 8481
report_ip_status -name ip_status 
upgrade_ip [get_ips  {XADC_ps7_0_axi_periph_0 XADC_xadc_wiz_0_0 XADC_rst_ps7_0_50M_0}] -log ip_upgrade.log
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - ProcessingSystem
Adding component instance block -- xilinx.com:ip:xadc_wiz:3.3 - XADC
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - ProcessorReset
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <XADC> from BD file </home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/XADC.bd>
Upgrading '/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/XADC.bd'
INFO: [IP_Flow 19-3422] Upgraded XADC_ps7_0_axi_periph_0 (AXI Interconnect 2.1) from revision 18 to revision 20
INFO: [IP_Flow 19-3422] Upgraded XADC_rst_ps7_0_50M_0 (Processor System Reset 5.0) from revision 12 to revision 13
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [IP_Flow 19-3422] Upgraded XADC_xadc_wiz_0_0 (XADC Wizard 3.3) from revision 5 to revision 6
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/XADC.bd> 
INFO: [BD 41-2124] The block design file </home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/XADC.bd> has changed from an XML format to a JSON format. All flows are expected to work as in prior versions of Vivado. Please contact your Xilinx Support representative, in case of any issues.
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/ip_upgrade.log'.
upgrade_ip: Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 7237.770 ; gain = 0.000 ; free physical = 3303 ; free virtual = 8477
export_ip_user_files -of_objects [get_ips {XADC_ps7_0_axi_periph_0 XADC_xadc_wiz_0_0 XADC_rst_ps7_0_50M_0}] -no_script -sync -force -quiet
update_compile_order -fileset sources_1
reset_run synth_1
reset_run XADC_processing_system7_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
WARNING: [BD 41-927] Following properties on pin /XADC/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=XADC_processing_system7_0_0_FCLK_CLK0 
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/XADC.bd> 
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/synth/XADC.vhd
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/sim/XADC.vhd
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hdl/XADC_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block ProcessingSystem .
INFO: [BD 41-1029] Generation completed for the IP Integrator block XADC .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ProcessorReset .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/ip/XADC_auto_pc_0/XADC_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block AXI_Lite/s00_couplers/auto_pc .
Exporting to file /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hw_handoff/XADC.hwh
Generated Block Design Tcl file /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hw_handoff/XADC_bd.tcl
Generated Hardware Definition File /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/synth/XADC.hwdef
[Sun Jun  2 21:17:55 2019] Launched XADC_processing_system7_0_0_synth_1, XADC_xadc_wiz_0_0_synth_1, XADC_rst_ps7_0_50M_0_synth_1, XADC_auto_pc_0_synth_1, synth_1...
Run output will be captured here:
XADC_processing_system7_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_processing_system7_0_0_synth_1/runme.log
XADC_xadc_wiz_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_xadc_wiz_0_0_synth_1/runme.log
XADC_rst_ps7_0_50M_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_rst_ps7_0_50M_0_synth_1/runme.log
XADC_auto_pc_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_auto_pc_0_synth_1/runme.log
synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/synth_1/runme.log
[Sun Jun  2 21:17:55 2019] Launched impl_1...
Run output will be captured here: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:01:21 ; elapsed = 00:01:20 . Memory (MB): peak = 7323.109 ; gain = 85.340 ; free physical = 3185 ; free virtual = 8399

I don´t see an error in the console and the IP core doesn´t have any error too. I just opened the project in 2019.1 and upgrade the IP, because it was a 2018.2 project (same procedure with the VTC project and the same error scheme).

So is there an issue with 2019.1 and some IP cores?

Error.png
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13 Replies
Xilinx Employee
Xilinx Employee
506 Views
Registered: ‎07-16-2008

回复: Strange synthesis error with Vivado 2019.1

Did you re-generate the block design after upgrading the IPs?

The screenshot shows error in XADC_xadc_wiz_0_0 OOC synth run. You may search the synth log to see if there're any more messages.

/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_xadc_wiz_0_0_synth_1/runme.log

 

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Don't forget to reply, kudo, and accept as solution.
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Explorer
Explorer
489 Views
Registered: ‎02-18-2013

回复: Strange synthesis error with Vivado 2019.1

Hello,

yes. I reset the output products, remove the HDL wrapper and create a new HDL wrapper and new output products. I got this error during the generation of the output products.

Output.png

With these log messages:

XADC_xadc_wiz_0_synth_1

*** Running vivado
    with args -log XADC_xadc_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source XADC_xadc_wiz_0_0.tcl


****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source XADC_xadc_wiz_0_0.tcl -notrace
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1388.762 ; gain = 2.016 ; free physical = 3291 ; free virtual = 7646
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/daniel/Schreibtisch/Git/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/Xilinx/Vivado/2019.1/data/ip'.
Command: synth_design -top XADC_xadc_wiz_0_0 -part xc7z010clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 5600 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1770.566 ; gain = 152.715 ; free physical = 3150 ; free virtual = 7506
---------------------------------------------------------------------------------
ERROR: [Synth 8-439] module 'XADC_xadc_wiz_0_0' not found
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.285 ; gain = 211.434 ; free physical = 3179 ; free virtual = 7535
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
6 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Mon Jun  3 09:11:17 2019...

XADC_XADC_0_synth_1

*** Running vivado
    with args -log XADC_XADC_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source XADC_XADC_0.tcl


****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source XADC_XADC_0.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1388.887 ; gain = 2.016 ; free physical = 3291 ; free virtual = 7646
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/daniel/Schreibtisch/Git/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/Xilinx/Vivado/2019.1/data/ip'.
WARNING: [Vivado 12-818] No files matched '/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/ip/XADC_XADC_0/XADC_XADC_0_ooc.xdc'
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Mon Jun  3 09:10:52 2019...

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Strange synthesis error with Vivado 2019.1

It looks to me that the files used for OOC synthesis are not ready.

Would you please go to project settings > IP? Under IP Cache, click "Clear Cache" and re-generate the block design?

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Explorer
Explorer
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Registered: ‎02-18-2013

回复: Strange synthesis error with Vivado 2019.1

Hello,

i have cleared the cache, but still the same issue

Console

config_ip_cache -clear_output_repo
config_ip_cache -clear_output_repo
save_bd_design
Wrote  : </home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/XADC.bd> 
regenerate_bd_layout
save_bd_design
reset_run synth_1
reset_run XADC_xadc_wiz_0_0_synth_1
reset_run XADC_XADC_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
INFO: [BD 41-1662] The design 'XADC.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/synth/XADC.vhd
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/sim/XADC.vhd
VHDL Output written to : /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hdl/XADC_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block ProcessingSystem .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ProcessorReset .
INFO: [BD 41-1029] Generation completed for the IP Integrator block XADC .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/ip/XADC_auto_pc_0/XADC_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block AXI_Lite/s00_couplers/auto_pc .
Exporting to file /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hw_handoff/XADC.hwh
Generated Block Design Tcl file /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hw_handoff/XADC_bd.tcl
Generated Hardware Definition File /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/synth/XADC.hwdef
[Mon Jun  3 10:42:32 2019] Launched XADC_xadc_wiz_0_0_synth_1, XADC_XADC_0_synth_1, XADC_auto_pc_0_synth_1, synth_1...
Run output will be captured here:
XADC_xadc_wiz_0_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_xadc_wiz_0_0_synth_1/runme.log
XADC_XADC_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_XADC_0_synth_1/runme.log
XADC_auto_pc_0_synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/XADC_auto_pc_0_synth_1/runme.log
synth_1: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/synth_1/runme.log
[Mon Jun  3 10:42:32 2019] Launched impl_1...
Run output will be captured here: /home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 7290.266 ; gain = 114.430 ; free physical = 3705 ; free virtual = 8064

XADC_xadc_wiz_0_0_synth_1

*** Running vivado
    with args -log XADC_xadc_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source XADC_xadc_wiz_0_0.tcl


****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source XADC_xadc_wiz_0_0.tcl -notrace
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1383.980 ; gain = 7.012 ; free physical = 2939 ; free virtual = 7299
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/daniel/Schreibtisch/Git/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/Xilinx/Vivado/2019.1/data/ip'.
Command: synth_design -top XADC_xadc_wiz_0_0 -part xc7z010clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 6581 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1769.723 ; gain = 152.715 ; free physical = 2410 ; free virtual = 6770
---------------------------------------------------------------------------------
ERROR: [Synth 8-439] module 'XADC_xadc_wiz_0_0' not found
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 1827.441 ; gain = 210.434 ; free physical = 2428 ; free virtual = 6789
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
6 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Mon Jun  3 10:43:36 2019...


XADC_XADC_0_synth_1

*** Running vivado
    with args -log XADC_XADC_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source XADC_XADC_0.tcl


****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source XADC_XADC_0.tcl -notrace
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1390.430 ; gain = 2.016 ; free physical = 2937 ; free virtual = 7297
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/daniel/Schreibtisch/Git/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/Xilinx/Vivado/2019.1/data/ip'.
WARNING: [Vivado 12-818] No files matched '/home/daniel/Schreibtisch/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/ip/XADC_XADC_0/XADC_XADC_0_ooc.xdc'
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Mon Jun  3 10:43:06 2019...
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Xilinx Employee
Xilinx Employee
455 Views
Registered: ‎07-16-2008

回复: Strange synthesis error with Vivado 2019.1

Did you validate the block design? Any problems reported?

There looks to be multiple XADC IP instances. And from the main log, impl_1 has been launched. It's not clear from the log files what is wrong.

Would you please archive the project and attach it for a look?

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Explorer
Explorer
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Registered: ‎02-18-2013

回复: Strange synthesis error with Vivado 2019.1

Hello,

yes I´ve validate the design and the tool doesn´t report any issue.

Validate.png

I have attached the XADC TCL script for you.

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Xilinx Employee
Xilinx Employee
415 Views
Registered: ‎07-16-2008

回复: Strange synthesis error with Vivado 2019.1

The single Tcl script is not enough to reproduce the issue. 

WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'xxx/BD_ip_gen/Git/IP'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
# set obj [get_filesets sources_1]
# set files [list \
# [file normalize "${origin_dir}/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hdl/XADC_wrapper.vhd" ]\
# ]
ERROR: [Vivado 12-172] File or Directory 'xxx/BD_ip_gen/Git/Zybo/Examples/XADC/XADC.srcs/sources_1/bd/XADC/hdl/XADC_wrapper.vhd' does not exist

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Explorer
Explorer
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Registered: ‎02-18-2013

回复: Strange synthesis error with Vivado 2019.1

I have archived the whole project for you.

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Xilinx Employee
Xilinx Employee
380 Views
Registered: ‎07-16-2008

回复: Strange synthesis error with Vivado 2019.1

I can only get these cells for the block design.

get_bd_cells -of_objects [get_bd_designs XADC]
/AXI_Lite /AXI_Lite/s00_couplers /AXI_Lite/s00_couplers/auto_pc /ProcessingSystem /ProcessorReset /XADC

There's no cell associated with one of the instances that fails OOC run - XADC_xadc_wiz_0_0.

By re-generating the block design, all OOC runs finish except 'XADC_xadc_wiz_0_0_synth_1'. I then go ahead and manally delete the run.

delete_runs XADC_xadc_wiz_0_0_synth_1

The subsequent top level synth and impl runs can complete successfully too.

bd_runs.png

 

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Explorer
Explorer
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Registered: ‎02-18-2013

回复: Strange synthesis error with Vivado 2019.1

Thanks, I will test it. But how can I regenerate the block design? Should I export and import it from TCL?

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Xilinx Employee
Xilinx Employee
346 Views
Registered: ‎07-16-2008

回复: Strange synthesis error with Vivado 2019.1

Click the "XADC" run in the Design Runs window, and select "Regenerate Output Products" from right-click menu. This will reset all the IPs within the BD and then you'll receive a pop-up to regenerate the block design.

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Explorer
Explorer
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Registered: ‎02-18-2013

回复: Strange synthesis error with Vivado 2019.1

Ok, I´ve opened the block design and run "Regenerate Output Products", so the XADC run was removed. After that I run "Generate Output Products"

Generate.png

Generate(2).png

But the Error still exists and I can not remove that runs

Run.png

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Adventurer
Adventurer
280 Views
Registered: ‎09-18-2018

回复: Strange synthesis error with Vivado 2019.1

Hi@kampi @graces 

you are not alone with your problem!

I also updated a XADC project from 2018.2 to 2019.1 and got the totally same errors.

So in my eyes it seems like no specific problems of you. Seems like something general! I also generated an older project (version 2017.4) to 2018.2 without problems. Doing the same steps from version 2018.2 to 2019.1 didn't worked!

I am also very interested for the problem solution

greetings,

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