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Registered: ‎10-07-2016

Sub-core references doesn't appear to like VHDL packages

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I have several modules that are common across my design. I'm using IPI. After looking at posts, this one seemed to be the best for help to use/define sub-cores:

https://forums.xilinx.com/t5/Design-Entry/HDL-files-used-in-custom-IP-could-not-be-updated-Advise-please/m-p/864773/highlight/true#M17129

 

So I packaged up the directory  of common VHDL files as a sub-core and added it into the file groups for the IP I'm packaging. It shows up as a sub-core with the right library name. I try synthesizing it and it fails. A VHDL package in the library is not found. The error states that "use.mylibrary.component_pkg" has an error and "component_pkg" is not found in the library. When I look at the .xml file, it all looks right: the library name, the file names, the synthesis group, the simulation group, at least as far as I my limited knowledge can determine. I'm not modifying the .xml at all. In the IP in which I want to use the common files, the subcore reference shows up in the packaging>file groups as "xilinx.com:ip:mylibrary:1.0" in both the Synthesis and Simulation groups.

 

I'm using 2017.1 on Windows 10.

 

What am I missing or need to do?

 

Thanks for your help ahead of time and have a great weekend,

 

 

Charlie

 

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Scholar
Scholar
935 Views
Registered: ‎04-26-2012

@chuck_s   "A VHDL package in the library is not found."

 

Just a hunch, but try issuing the following tcl command before packaging your shared files as a 'library core' :

set_property source_mgmt_mode DisplayOnly [current_project]

You will probably also then need to repackage your IP that uses the 'sub-core reference' after making the above change.

 

EDIT (clarify) : This flag forces the Vivado IP packager to include all the source files, rather than omitting some that Xilinx's buggy source parser mistakenly thinks are unused, see AR 70646 :

"
" With this option, the hierarchy in the Vivado Hierarchy Source View will still be displayed based on the

" default value of generics and parameters, but all source files in the project will be sent to the IP packager.

"


To help troubleshoot, could you post the following:

 

'Library core' info:

  - VHDL code snippets of your shared package with the package header, and a declaration of a problematic item

  - screenshot of the IP Packager 'File Groups' page during the  'package as a library core' process

 

IP info:

  - VHDL code snippets of the IP library clause for the 'sub-core reference', and an instance of a problematic item

  - screenshot of the IP Packager 'File Groups' page during the packaging of your IP core

 

Top level info:

  - from your top level project, a screenshot of the "IP catalog"  tab showing your user repository with your IP core

 

-Brian
 

 

 

 

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Scholar
Scholar
936 Views
Registered: ‎04-26-2012

@chuck_s   "A VHDL package in the library is not found."

 

Just a hunch, but try issuing the following tcl command before packaging your shared files as a 'library core' :

set_property source_mgmt_mode DisplayOnly [current_project]

You will probably also then need to repackage your IP that uses the 'sub-core reference' after making the above change.

 

EDIT (clarify) : This flag forces the Vivado IP packager to include all the source files, rather than omitting some that Xilinx's buggy source parser mistakenly thinks are unused, see AR 70646 :

"
" With this option, the hierarchy in the Vivado Hierarchy Source View will still be displayed based on the

" default value of generics and parameters, but all source files in the project will be sent to the IP packager.

"


To help troubleshoot, could you post the following:

 

'Library core' info:

  - VHDL code snippets of your shared package with the package header, and a declaration of a problematic item

  - screenshot of the IP Packager 'File Groups' page during the  'package as a library core' process

 

IP info:

  - VHDL code snippets of the IP library clause for the 'sub-core reference', and an instance of a problematic item

  - screenshot of the IP Packager 'File Groups' page during the packaging of your IP core

 

Top level info:

  - from your top level project, a screenshot of the "IP catalog"  tab showing your user repository with your IP core

 

-Brian
 

 

 

 

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Participant
Participant
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Registered: ‎10-07-2016

That was it.

 

Thanks for taking the time to look at this and offering a suggestion. I definitely appreciate your effort.

 

I've looked for that property on the forum and found this which I'm sure you know about:

https://www.xilinx.com/support/answers/69320.html

 

- Chuck_S

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