04-06-2009 10:24 AM
Hi, I need to support an old xc4013e device. We've won a contract to upgrade a design to a new FPGA, but first we have to prove the vhdl files given to us are the correct ones. I know ise 4.2i will support the xc4000e family, but this is edif only, no VHDL. I've checked out 3rd party suppliers, mentor graphics etc, but non of them have tools sets to support this device. Does any body have any thoughts to how I can synth a vhdl design for an xc4013e?
04-06-2009 11:23 AM
You could always find someone who still has a running copy of the 4.2 or older tools (I have
Foundation 4.1i with a license for VHDL / Verilog) and contract out the test. What are you
trying to accomplish? If you need to be sure that the binaries for the old parts match the
VHDL, even having the same tools won't help unless you have all of the settings used
to generate the original bit files. If you just want to show that the VHDL you have runs
in the older parts, perhaps you could build an EDIF netlist with some newer tools and
generate the bit file from that with the older ISE.
04-06-2009 12:42 PM
Hi Gabor, We're trying to prove the functionailty of the source code be for moving the design to a new FPGA. Its not a high speed design, or time cirtical, or even complicated It more for the customer, so that they can be sure that the code they have is what they think it is (version control wasn't so hot in the days this was done). we don't have to compare the orginal bit file, we have a working unit that we can test on.
Thanks for the advise, I'll give the EDIF / old ISE route ago.
04-07-2009 06:20 AM
Hi, how do I generate an edif from with in ISE? I can't seem to find the right options, having never need to generater an edif before
04-09-2009 03:51 AM