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Participant jbonanno1
Participant
8,329 Views
Registered: ‎01-11-2015

System Verilog Packed Arrays on Port List

I have a port list some like this:

 

import DATA_TYPES::*;

 

module Transmit (

input logic CLK,

input logic RST,

input packet_t packet,

output logic[1:0] TXD,

output logic         TXEN

);

 

.... where I take in the packet type that is defined in package DATA_TYPES as ..

 

typedef struct packed {

header;

msg_id;

data;

crc} packet_t

 

Essentially, as long as I place module transmitter at the top level hierarchy of the design, everyting is fine.

As soon as I wrap another file around transmitter, so that the transmitter module is 2 more layers down

int the hierarchy from where the top level design file is, Vivado says that the drivers for module port "packet"

do not exist...

 

This is very frustrating, implying limited support for System Verilog structures on the port list.

 

James

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2 Replies
Participant jbonanno1
Participant
8,327 Views
Registered: ‎01-11-2015

Re: System Verilog Packed Arrays on Port List

The title of this post should be "Packed Structures on Port List"
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Participant jbonanno1
Participant
8,324 Views
Registered: ‎01-11-2015

Re: System Verilog Packed Arrays on Port List

typedef struct packed {

logic [31:0] header;

logic[31:0] msg_id;

logic[32][31:0] data;

logic[31:0] crc } packet_t
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