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Registered: ‎07-30-2020

System Verilog syntax error HDL 9-806 with simple conditional if elsif else statement

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An HDL 9-806 syntax error occurs with the following simple system verilog module, on lines 9 and 10. It goes away when I remove line 9. This happens in Vivado 2020.1 on a Linux system, and is repeatable with a new project.

The syntax in this example follows exactly what is listed in UG-901, in chapter 8's section called "Conditional if-else Statement."

What is being done wrong?

Module code:

module mytest (
    input logic clk,
    input logic testInput1,
    input logic testInput2,
    output logic testOutput
);
    always @(posedge clk) begin
        if(testInput1 == 1) testOutput <= 1;
        elsif(testInput2 == 1) testOutput <= 1;
        else testOutput <= 0;
    end
endmodule

 

...and the errors:

[HDL 9-806] Syntax error near "testOutput". ["/mypath/test.sv":9]

[HDL 9-806] Syntax error near "else". ["/mypath/test.sv":10]

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Scholar
Scholar
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Registered: ‎09-16-2009

Quite simply, SystemVerilog does not have an elsif statement.

It's a little confusing in that the precompiler DOES define a `elsif.

But there's no equivalent procedural code for a direct else if.

However it's still just as easy:

 

if (expression) statement;
else if (expression) statement;
else if (expression) statement;
else statement;

 

(Edit to add): Checking UG901 - it appears those examples in the document are just plain wrong.  As I said, I'm fairly certain there's no elsif statement in the language.

Regards,

Mark

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Scholar
Scholar
320 Views
Registered: ‎09-16-2009

Quite simply, SystemVerilog does not have an elsif statement.

It's a little confusing in that the precompiler DOES define a `elsif.

But there's no equivalent procedural code for a direct else if.

However it's still just as easy:

 

if (expression) statement;
else if (expression) statement;
else if (expression) statement;
else statement;

 

(Edit to add): Checking UG901 - it appears those examples in the document are just plain wrong.  As I said, I'm fairly certain there's no elsif statement in the language.

Regards,

Mark

View solution in original post

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Scholar
Scholar
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Registered: ‎09-16-2009

@someone_at_xilinx

It would be good to issue a CR to fix the documentation in UG901 to remove these examples.  They are not legal SystemVerilog.

(I've got a nagging feeling that maybe I'm missing something from the SystemVerilog spec, but my read of the 1800-2012 spec only shows the `elsif.  There's no procedural equivalent as the examples in UG901 show)

Regards,

Mark

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