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Adventurer
Adventurer
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Registered: ‎05-12-2017

[SystemVerilog] Are there predefined AXI interfaces

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I've implemented an AXI IP but to avoid problems with repetition I defined AXI interface. However if I try to use it in IP Package it chockes claiming it is already in interface. Is there a way I can reuse predefined interfaces in SV?

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Adventurer
Adventurer
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Registered: ‎05-12-2017

Re: [SystemVerilog] Are there predefined AXI interfaces

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@muzaffer Thanks. I can no longer repro the issue in 2017 version. I think it was a missing feature from 2016 which I used due to my misunderstending of licensing.

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Teacher
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Registered: ‎03-31-2012

Re: [SystemVerilog] Are there predefined AXI interfaces

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@mpiechotka if the interfaces you want are implemented in a package you can just import it. 

Also  before doing anymore work on writing your own axi interfaces, check out the new xilinx axi verification ip. They might include synthesizable interfaces too (this is something I have yet to do I am afraid).

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Adventurer
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Registered: ‎05-12-2017

Re: [SystemVerilog] Are there predefined AXI interfaces

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@muzaffer I see that they are in the 'Package IP' interface but I cannot find a package name?

Re verification ip: I assumed this is for testing the design, not use in components.
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Adventurer
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Re: [SystemVerilog] Are there predefined AXI interfaces

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As a clarification - by interface I meant a SystemVerilog concept, not IP Packager interface or IP core.
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Teacher
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Re: [SystemVerilog] Are there predefined AXI interfaces

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@mpiechotka I understand that you want a SV interface which implements an AXI bundle. This is quite commonly done. 

Can you show the error you are receiving when you try to use your code? This might point to the package which you can use.

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Adventurer
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Registered: ‎05-12-2017

Re: [SystemVerilog] Are there predefined AXI interfaces

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@muzaffer Thanks. I can no longer repro the issue in 2017 version. I think it was a missing feature from 2016 which I used due to my misunderstending of licensing.

View solution in original post

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