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Explorer
Explorer
6,099 Views
Registered: ‎02-24-2016

[SystemVerilog] generate for assign -> why doesn't work?

Hi All,

 

I'm receiving the "[Synth 8-2599] range is not allowed in a prefix" error message for the following code:

 

genvar i;
generate for (i=0; i<5; i=i+1) begin
    assign mem_data[15:0][i] = tg_data[15:0][i];
  end
endgenerate

Why?

 

Here are the signal declarations:

 

wire [15:0] tg_data [15:0]
output [15:0] mem_data [15:0]

Could the generate statement be used for assign statement? How? Please provide an example.

 

Thank you

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Guide
Guide
6,091 Views
Registered: ‎01-23-2009

This has nothing to do with the generate statement, the base assign statement is illegal

 

assign mem_data[15:0][0] = tg_data[15:0][0];

 

This is attempting to tie the least significant bit of all 16 words of mem_data to bit 0 of all 16 words of tg_data. 

 

I am not sure what you are trying to do with your loop - tie the LSB 5 bits of all 16 words together? If so, then turn the loop around

 

 

genvar i;
generate for (i=0; i<16; i=i+1) begin
    assign mem_data[i][4:0] = tg_data[i][4:0];
  end
endgenerate

 

 (But this seems like really weird code to do in an assign - what are you expecting to happen to the remaining 11 bits of each of the 16 words - are you going to 'assign' them in another process?)

 

Avrum

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