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Newbie
Newbie
8,672 Views
Registered: ‎07-18-2016

SystemVerilog import VHDL package error

Hello,

 

I have a SystemVerilog (.sv) testbench that instantiates VHDL (.vhd) design files. In the testbench, I need to use a record defintion from a VHDL package file. When I try to import pkg::*; in the .sv testbench, Vivado gives an error during compilation:

 

xvlog -m64 --relax -prj sw_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "tb.sv" into library xil_defaultlib
ERROR: [VRFC 10-91] pkg is not declared [tb.sv:3]

I changed the compile order in the Vivado window so the pkg.vhd file is compiled before tb.sv, however this error still persists. I've also tried `including the .vhd package file instead of importing, however that generates a syntax error as they are different language files.

 

Any ideas?

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Xilinx Employee
Xilinx Employee
8,662 Views
Registered: ‎10-24-2013

Hi @marver

Can you please post simple code that demonstrates your usage for better understanding?

Thanks,Vijay
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Newbie
Newbie
8,660 Views
Registered: ‎07-18-2016

Hi @vijayak,

 

  Here's a snippet of tb.sv

`timescale 1ps/100fs

import pkg::*;

module tb;
  local_bus_record sys_ctrl_bus;
  //...
endmodule

and here's a snippet of the pkg.vhd file

library ieee;
use ieee.std_logic_1164.all;

package pkg is
  type local_bus_record is record
    reg_ack  : std_logic;
    reg_data : std_logic_vector(31 downto 0);
  end record local_bus_record;
end;
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Xilinx Employee
Xilinx Employee
8,625 Views
Registered: ‎10-24-2013

Hi @marver

 

I am able to reproduce the issue with Vivado and seeing the same issue with Questa as well.

I will get back to you soon on this.

Thanks,Vijay
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Visitor
Visitor
4,746 Views
Registered: ‎01-16-2017

What was the solution/outcome here? I'm having an identical issue in 2016.2

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Observer
Observer
2,949 Views
Registered: ‎07-03-2017

Hi

Is there a solution to that problem yet?

and in general - how well xilinx tools work both with VHDL and Verilog/SystemVerilog files?

 

oft