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Visitor ldm_as
Visitor
135 Views
Registered: ‎09-04-2019

[SystemVerilog] import packages -> instead of passing parameters?

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Hi All,

As for importing the SystemVerilog packages, could this replace passing the parameters while instantiation of one module into another? 

What's the scope of importing the packages? As for include files, the scope is just the current hierarchy (where they were included from). But what's about the imported packages?  

Thank you!

 

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Xilinx Employee
Xilinx Employee
97 Views
Registered: ‎05-22-2018

Re: [SystemVerilog] import packages -> instead of passing parameters?

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Hi @ldm_as ,

I guess, packages can be imported into the current scope where items in that package can be used.

Also note that the items within the packages cannot have hierarchical references to identifiers except those created within the package or made visible by the import of another package.

Regarding avoiding importing parameters, i think you can use the feature of importing the specific definations from the package, for instance:

package my_pkg;
  typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } signal;
  typedef struct { bit [3:0] signal_id;
                     bit       active;
                     bit [1:0] timeout; 
                   } e_sig_param;
 
  function common ();
      $display ("Called from somewhere");
     endfunction
 
    task run ( ... );
      ...
    endtask
endpackage

import my_pkg::GREEN;
import my_pkg::signal;
import my_pkg::common;

There is one nice blog(I personally found good) on Import Package and `Include, please have a look:

https://blogs.mentor.com/verificationhorizons/blog/2010/07/13/package-import-versus-include/

Hope the provided info will be helpful.

Thanks,

Raj 

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Xilinx Employee
Xilinx Employee
98 Views
Registered: ‎05-22-2018

Re: [SystemVerilog] import packages -> instead of passing parameters?

Jump to solution

Hi @ldm_as ,

I guess, packages can be imported into the current scope where items in that package can be used.

Also note that the items within the packages cannot have hierarchical references to identifiers except those created within the package or made visible by the import of another package.

Regarding avoiding importing parameters, i think you can use the feature of importing the specific definations from the package, for instance:

package my_pkg;
  typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } signal;
  typedef struct { bit [3:0] signal_id;
                     bit       active;
                     bit [1:0] timeout; 
                   } e_sig_param;
 
  function common ();
      $display ("Called from somewhere");
     endfunction
 
    task run ( ... );
      ...
    endtask
endpackage

import my_pkg::GREEN;
import my_pkg::signal;
import my_pkg::common;

There is one nice blog(I personally found good) on Import Package and `Include, please have a look:

https://blogs.mentor.com/verificationhorizons/blog/2010/07/13/package-import-versus-include/

Hope the provided info will be helpful.

Thanks,

Raj 

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