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Visitor boffin
Visitor
8,983 Views
Registered: ‎01-06-2013

Systemverilog to Verilog translation

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I have a code block (multiple files) in Systemverilog. I am using the Xilinx tool flow that does not understand SystemVerilog (an old part). Is there a tool (or a rule book) I can use to convert the SystemVerilog to standard Verilog-2001 code ?

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Moderator
Moderator
13,971 Views
Registered: ‎06-05-2013

Re: Systemverilog to Verilog translation

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Hi Boffin,

 

There is no such xilinx tool which convert the system verilog file to verilog file.You have to manually change the code.

If you want to run system verilog file then use vivado.It supports system verilog.

 

Thanks

 

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Moderator
Moderator
13,972 Views
Registered: ‎06-05-2013

Re: Systemverilog to Verilog translation

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Hi Boffin,

 

There is no such xilinx tool which convert the system verilog file to verilog file.You have to manually change the code.

If you want to run system verilog file then use vivado.It supports system verilog.

 

Thanks

 

--------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Xilinx Employee
Xilinx Employee
8,936 Views
Registered: ‎09-20-2012

Re: Systemverilog to Verilog translation

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Hi Rahul,

 

If your query is answered, please mark the thread as solved.

 

Regards,

Deepika.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Historian
Historian
8,897 Views
Registered: ‎01-23-2009

Re: Systemverilog to Verilog translation

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The third party synthesis tools (Mentor Precision and Synopsys Synplify) both support SystemVerilog, and (I am pretty sure) will target any device, including very old ones. Once the design is synthesized, the resulting edif netlist can be imported into the ISE implementation tools - it is irrelevent at that point whether the edif came from Verilog, SystemVerilog or VHDL RTL files.

 

Avrum

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