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14,990 Views
Registered: ‎07-03-2009

Tcl error when running MIG in a newly-created project

Hi, I'm having difficulty getting a sample DDR2 memory controller, using a Xilinx starter kit. I've got a Spartan 3A Starter Kit, and I'm trying to create a memory interface for the on-board DDR2 memory using MIG. Following the instructions in the MIG User's Guide section titled "Implementing MIG Designs in ISE GUI Mode", I've created a new project called ddr2test, and a new IP Core using MIG called memctrl. On the MIG options screen, I've selected "Create Design for Xilinx Reference Boards," then I select the Spartan 3A Starter Kit from the drop down menu.

 

After clicking through the remaining screens and pressing the Generate button, I get this error in the console window:

 
ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "::memctrl_xmdf::xmdfInit"'.

 

Where "memctrl" is the name of the module I tried to create with MIG. Nothing gets added to my project file, so I can't simply ignore the error. It also seems to crash MIG, and leaves a coregen_lock file in the ipcore directory that must be manually deleted before I can run it again.

 

I was previously getting this error using ISE WebPack 11.1 and MIG 3.0. I've since upgraded to 11.2 and MIG 3.1, but still get the same error. This is on a Windows XP machine, if that matters.

 

Any suggestions? This is plain vanilla project, created from scratch, for a reference board, so I'm not sure what I might be doing wrong.

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17 Replies
Xilinx Employee
Xilinx Employee
14,975 Views
Registered: ‎10-23-2007

Re: Tcl error when running MIG in a newly-created project

Have you filed a support case on this?  Clearly you are hitting a bug that most others do not see.  There's either something about your settings or (lower probability) something in your environment that MIG doesn't like.  Does MIG generate a datasheet.txt file?  If so, you could post it here so that your settings can be duplicated to see if the problem exists on other systems.

 

My other suggestion is to use the "Board Files" option in MIG instead of "Create Design" which will instead give you a zip file with all the files for the S3A starter kit directly.  MIG is better at creating a design for a new board than adapting its output to an existing board, but it can be done.  In this case, however, the board files is a quicker solution.

 

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14,975 Views
Registered: ‎07-03-2009

Re: Tcl error when running MIG in a newly-created project

Thanks for the suggestions! I did request access to WebCase to file a support request, but haven't been granted access yet.

 

MIG generates a datasheet.txt file in .\memtest\ipcore_dir\memctrl\example_design\datasheet.txt, but the file simply says "Xilinx Reference Boards for spartan3a are generated successfully".

 

I have also tried the "board files" option you suggested, but ran into another problem. I used the create_ise.bat script in .\memtest\ipcore_dir\memctrl\board_files\sp3a_board_files\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par, to create a new test.xise project that could be opened with ISE WebPack. When I opened this and tried to implement the top module, I got hundreds of warnings (possibly normal?), and finally an error saying that I needed a ChipScopePro license. I know MIG can be set to omit ChipScope support when creating a new design, but since this is a customized reference design specifically for the Spartan 3A starter kit, I think I'm out of luck.

 

The last thing I tried was to create a new MIG design, but selecting the exact FPGA and SDRAM that's on the Spartan 3A starter kit board. This allowed me to omit the ChipScopePro support. I'm not confident this would even work, since the readme.txt from the Spartan 3A starter kit reference design says that the rtl output of MIG had to be hand-tweaked to support that board's pins and other details. Nevertheless, I wanted to give it a try. The MIG wizard worked, but only added a single .xco file to my project. From there, I added all the example_design rtl files and ucf to my project, but when I tried to implement it, I got lots of errors about non-existant nets referenced in the ucf. So then I tried running the create_ise.bat script again, opening the resulting test.xise project file, and implementing that. That succeeded, albeit with hundreds of warnings. Of course the pin assignments of that design didn't match the Spartan 3A starter kit, and I wasn't able to figure out how to change them. I know MIG has an "Update Design" option for this purpose, but I couldn't figure out how to re-run MIG in order to get to it. The memctrl.xco (which I think is meant for this purpose) isn't added to the test.xise project file by default, and when I added it, I started getting implementation errors again about non-existent nets. 

 

Is there a MIG tutorial for newbs that you would recommend? I've read/skimmed most of the MIG manual (600 pages!), and viewed the Xilinx MIG video, but they're all pretty vague on the actual steps needed to set up a "hello world" sort of SDRAM example for the starter kit using ISE WebPack.

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14,955 Views
Registered: ‎07-03-2009

Re: Tcl error when running MIG in a newly-created project

Arghh, Xilinx just denied my request to create a WebCase account for support. I’d registered as a student, which seemed the closest thing to hobbyist or non-commercial. Now I'm unsure how I'll ever get this problem resolved. Should I go back and lie, and claim to be Chief Hardware Engineer at HyperGlobalMegaCorp?
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Xilinx Employee
Xilinx Employee
14,950 Views
Registered: ‎11-28-2007

Re: Tcl error when running MIG in a newly-created project


steve.chamberlin wrote:

I have also tried the "board files" option you suggested, but ran into another problem. I used the create_ise.bat script in .\memtest\ipcore_dir\memctrl\board_files\sp3a_board_files\sp3a_board_files\ddr2_sdram\verilog\vlog_bl8\example_design\par, to create a new test.xise project that could be opened with ISE WebPack. When I opened this and tried to implement the top module, I got hundreds of warnings (possibly normal?), and finally an error saying that I needed a ChipScopePro license. I know MIG can be set to omit ChipScope support when creating a new design, but since this is a customized reference design specifically for the Spartan 3A starter kit, I think I'm out of luck.



To implement the S3A board design without chipscope license, you can open the file vlog_bl8.v and comment out the instantiations of chipscope cores icon, ila and via.

 

Cheers,

Jim

 

Cheers,
Jim
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Newbie abionnnn
Newbie
14,341 Views
Registered: ‎10-21-2009

Re: Tcl error when running MIG in a newly-created project

I seem to be able to reproduce this bug

 

ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "::memtest_xmdf::xmdfInit"'.
Tcl_ErrnoId: unknown error
Tcl_ErrnoMsg: No error
_cmd: ::xilinx::Dpm::dpm_chCreateNewSource $piThisInterface
errorInfo: invalid command name "::memtest_xmdf::xmdfInit"

 

This is using Xilinx ISE Webpack 11.1. Will upgrading to 11.3 help? My board is a Spartan-3E...

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Participant keithxilinx1
Participant
13,900 Views
Registered: ‎02-15-2009

Re: Tcl error when running MIG in a newly-created project

I was able to reproduce on ISE 11.4 with MIG 3.3 on a Spartan 3E reference design.

 

I filed a support ticket just now, hopefully this might get resolved.

 

In the interim, did anyone find a fix/workaround?

 

Thanks

 

Keith

 

Newbie kustarev
Newbie
13,776 Views
Registered: ‎01-18-2010

Re: Tcl error when running MIG in a newly-created project

Have the same problem using ISE 11.4 both on Linux and Windows when generating core for Xilinx reference board.

 

ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "::migctl_xmdf::xmdfInit"'.
Tcl_ErrnoId: unknown error
Tcl_ErrnoMsg: Success
_cmd: ::xilinx::Dpm::dpm_chCreateNewSource $piThisInterface
errorInfo: invalid command name "::migctl_xmdf::xmdfInit"
while executing
"::${moduleName}_xmdf::xmdfInit aInstance"
(procedure "::utilities_xmdf::xmdfGetOutputList" line 18)
invoked from within
"::utilities_xmdf::xmdfGetOutputList $sModule $sFilesDir _XmdfOutputList"
(procedure "dpm_coregenGetOutputList" line 21)
invoked from within
"dpm_coregenGetOutputList $sCoreModuleName $iProject $sCoreDir _genList"
(procedure "dpm_coregenCreateCore" line 97)
invoked from within
"$_sCreate $sFilePath $iNewSourceComp lOutputFileList"
(procedure "::xilinx::Dpm::dpm_chCreateNewSource" line 58)
invoked from within
"::xilinx::Dpm::dpm_chCreateNewSource $piThisInterface"
Message Edited by kustarev on 01-18-2010 11:10 AM
Xilinx Employee
Xilinx Employee
13,767 Views
Registered: ‎10-23-2007

Re: Tcl error when running MIG in a newly-created project

Can you be a little more specific about the steps you are following to get this error?  Is this from within ProjectNavigator?

 

You might try the following:

 - run Coregen from the Windows start menu (not through Project Navigator)

 - run MIG within Coregen and choose the reference board option

 - exit Coregen

 - unzip the resultant zip file

 - start ProjectNavigator and import the specific design files from the zip file into your design

 

Good luck.

 

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Participant keithxilinx1
Participant
13,759 Views
Registered: ‎02-15-2009

Re: Tcl error when running MIG in a newly-created project

Hey,

 

Thanks for taking the time to respond.

 

This .tcl error was as a result of trying to load a file from the root folder directory called <component_name>.xco, in my case mig33.xco.  This file is NOT useful and should not be loaded.  gsazacks (sorry, sp!) was nice and emailed me telling me that MIG is very wierd in the coregen world, and that the output is SOURCE, not a blackbox simply-call-me-ready-to-go module.

 

 

I should have replied earlier and closed this, but I was trying to put together something definitive instead of sort of 1/2 an answer.

 

The first steps are definitely right:

 

 - run Coregen from the Windows start menu (not through Project Navigator) [ed: I don't think this matters from what I can tell]

 - run MIG within Coregen and choose the reference board option

 - exit Coregen

 - unzip the resultant zip file

 

 But you can't simply import the specific design files and run with them.  The main reason for this is because there are tons of project options that need to get set for MIG to completely compile/synthesize/P&R/whatever.

 

Next steps,

 

- run create_ise.bat from inside par directory

- resultant file is called "test.xise", there is a test.ise that is also created for older versions of ISE (aka not 11.x)

- inside project navigator, load test.xise.

- edit vlog_bl2cl25.v, and comment out the instantiations that begin with "icon my_icon", "ila my_ila", and "vio my_vio ".  Otherwise you'll see DEBUG_SIGNALS_INST or something like that on synthesis.  These are all for chipscope, and if you know how to use this, you really don't need my help.

- Then you should be able to synthesize the code.

 

Some notes:

 

- the test bench is synthesizable.  It's odd. Most testbenches are JUST for simulation.  This one will synthesize and run on hardware.

 

- you'll want to completely replace the testbench with your own code.  This is sort of the "hook" into the memory controller.

 

- The included design includes a DCM to shift the provided clock and provide both 0 degrees and 90 degree signals.  This DCM DOES NOT, however, provide the actually clock necessary to get this thing to work.  The test bench expects a 80-170mhz clock just to function on A10, the SMA connector on the right hand side of the board.  But the spartan-3e starter kit only has a 50mhz clock onboard.  You can try using that, it seems to function, however probably not reliably.  So you can instantiate ANOTHER DCM, and attach THAT DCM to the MIG DCM, and generate a 2X clock from the 50mhz, and get a 100mhz for the testbench.  You need to delete the IBUF that connects on the input of the MIG provided DCM or you will get "MULTIPLE DRIVERS" on synthesis.  A co-worker expert tells me connecting two DCMs like this might not be a great idea, and suggested routing the first DCM offboard, and then bring it back on the board. YMMV.

 

- The documentation in UG086 is just plain wrong in a bunch of places, mainly in reference to the whole FLOW of loading all this stuff.  There is no user_design folder, no docs folder, and so on.  There is no option for them to add the DCM necessary to generate the clock.

 

 I actually have NOT yet had a chance to create my own testbench to replace theirs yet.  This requires me to have a better understanding than I do to figure out how to drive the controller.  I don't think it's hard, but there's simply a lot to know to using this.

 

On another hand, and this is probably good for another post, using block rams is 2903489203483498 % easier but maxes out around 45k bytes.  You can use distributed ram (the LUTs), but you can't get much more than 10k bytes(IIRC) or so on the Spartan-3e board.

 

Hope this helps someone.

 

Keith

 

Instructor
Instructor
9,779 Views
Registered: ‎08-14-2007

Re: Tcl error when running MIG in a newly-created project

Keith wrote:

 

 - run Coregen from the Windows start menu (not through Project Navigator) [ed: I don't think this matters from what I can tell]

 

The reason I said to run from the start menu is that (at least in ISE 10.1) starting from the project

Navigator via "Project --> New Source" bypasses the Core Generator GUI and goes right to the

core customization screen.  At least in the case of MIG, you cannot set the language generation

options within the customization screen (i.e. I wanted Verilog, it defaulted to VHDL with no place

to change it), so you need to set this in the CoreGen project options.  I think once you've done

this within an ISE project, the Coregen project options are remembered for the next core.

 

Another point was that since you don't want the .xco file in your ISE project, using a separate Coregen project

for the MIG core makes it easier to go back and re-customise if necessary.  This is also quite useful on a

custom board where you might need to run through more than once to get the pinouts right.

 

- The documentation in UG086 is just plain wrong in a bunch of places, mainly in reference to the whole FLOW of loading all this stuff.  There is no user_design folder, no docs folder, and so on.  There is no option for them to add the DCM necessary to generate the clock.

 

I used MIG 2.1, 2.2, and 2.3 and all seemed to match UG086.  My guess is that either the flow changes for

"prebuilt" designs for the reference boards, or else something has seriously changed in MIG 3.x versions.

My experience has only been for my own custom boards, so I had to go through the entire customization

process and did end up with the aforementioned directories and files.

 

Many thanks to Keith for taking the time to write up this procedure.  Using Xilinx reference designs, especially

complex ones like DDR memory controllers, can be a daunting task.  Starter kit users, in particular are often

less experienced with Xilinx flow in general, and can benefit from more detailed core usage instructions.

 

Regards,

Gabor

 

 

-- Gabor
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Participant keithxilinx1
Participant
9,772 Views
Registered: ‎02-15-2009

Re: Tcl error when running MIG in a newly-created project


gszakacs wrote: 

I used MIG 2.1, 2.2, and 2.3 and all seemed to match UG086.  My guess is that either the flow changes for

"prebuilt" designs for the reference boards, or else something has seriously changed in MIG 3.x versions.

My experience has only been for my own custom boards, so I had to go through the entire customization

process and did end up with the aforementioned directories and files.

 

 

Many thanks to Keith for taking the time to write up this procedure.  Using Xilinx reference designs, especially

complex ones like DDR memory controllers, can be a daunting task.  Starter kit users, in particular are often

less experienced with Xilinx flow in general, and can benefit from more detailed core usage instructions.

 

Regards,

Gabor

 

 


Gabor,

 

Yes, the flow does in fact change for the "prebuilt" boards.  You get almost no options whatsoever with "reference board" selection.  I also tried things manually, and of course, you do have a number of options, and yes, you get the files as described in UG086.  For the starter boards, I don't think there's a practical way(and perhaps much benefit!) of doing this manually.

 

I had a lengthy discussion with Xilinx tech support, who were helpful, and they promised to file a CR to include better documentation (and correct the existing problems) in UG086 in regards to integrating MIG cores into your own design when using the starter boards.

 

It was only with your help, the forums, and a friend that I was able to hack together a solution.

 

You hit the nail on the head!  The exact people, starter kit buyers, who need to rely on correct documentation and easy solutions, are the ones who are currently disadvantaged.  UG086 describes mostly the "manual" process, and does not include detailed instructions on how to integrate the output start kit board files, that are output from MIG as a ZIP FILE, btw. :)

 

Thanks

 

Keith

 

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Newbie kustarev
Newbie
9,764 Views
Registered: ‎01-18-2010

Re: Tcl error when running MIG in a newly-created project

 

Thanks, it works.

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Newbie tesloev
Newbie
9,697 Views
Registered: ‎02-07-2010

Re: Tcl error when running MIG in a newly-created project

Thanks Keith,

 

Your post helped me to sythesise & test successfully, the sample DDR controller arch for Spartan 3E-1600, generated by MIG 3.0 on ISE 11.1  ( host OS - Ubuntu 9.04 )

I just had to change some name in a set_ise_prop.tcl file (http://www.xilinx.com/support/answers/32615.htm) in order to be able to run successfully create_ise.bat

 

Regards,

 

Stoytcho

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Visitor alphalas
Visitor
9,656 Views
Registered: ‎12-22-2009

Re: Tcl error when running MIG in a newly-created project

First of all I want to thank Keith for the information. But I also would like to post my comments on that topic.

I think that customers are simply too patient or have too much time to rewrite and correct extremely complicated code that is advertised to work. When I bought a Spartan 3E Starter Kit (and I emphasize that the word is Starter, not Expert) I expect that the board has been designed and revised by Xilinx experts and I expect to be able to use all of the components on that board. I want to emphasize that the board is being sold by Xilinx since 2006 (refering to the docs). I also expect to get some example code with a starter board from the market leader. But unfortunately the reference designs for the board were the first strange thing. Instead of getting some VHDL or Verilog example code as I had expected, all reference designs use a PicoBlaze or MicroBlaze (which is not free!) softcore processor. The PicoBlaze has to be programmed in assembler and eliminates all the parallel processing capabilities of FPGAs and HDLs. So I asked myself why I bought an FPGA board and not a simple microcontroller board...

Now I come to my main RAM access problem: One of the main features of this board are the 512Mbit of DDR SDRAM. So I looked for a memory controller. Looking at all the Xilinx marketing docs and all the introductory videos done for the Memory Interface Generator (MIG) which is available in version 3.3 now, a customer expects that this core generator must be able to work at least with Xilinx' own development boards. I emphasize that the MIG videos even refer to the reference boards.

I bought the Spartan 3E Starter board just to find out that it does NOT work as expected, which means that there is simply NO way to use the memory on that board as is. It's like buying a car and telling you that one of the main features is there but actually can't be used.
I use ISE 11.4 Webpack. I ran the MIG, selected my reference board, but instead of getting a generated core which is ready to be used (and is what I expect from a core generator) I got a zip file. Actually I had to find out that a zip file has been created after wondering why nothing appeared in my project. After extracting the file and looking at the textfiles which seem to have been written in hurry and are spread throught the subfolders I came to the next surprise I would call a real desaster - you need an external clock source (!) connected via SMA cable in order to be able to use the memory, i.e. it is not possible to use the memory as is on the board with the MIG reference design. The board docs don't say anything about that!
The next surprise is in the docs which state strange things: "There were several hand-modifications to the rtl and simulation files required to do to the core targetted on the Spartan-3E Starter Kit board." This simply means that the board is NOT compatible with the MIG and with the memory design guidelines. The MIG output has been hacked in order to be made somehow compatible with the board. If this modification is ok and works as expected is another question. This incompatibility explains why you get the zip files containing a premade project and are not able to use the MIG as advertised to create your own design. The included files also say things like: "While the actual board loopback length is normally a critical measurement for proper operation of the controller, the loopback was not designed on this board." or "The net control0_rst_dqs_div should be placed in the center of the data bank. Instead in Spartan-3E starter kit this signal placed in different bank, As a result the delay on this signal is more than the expected delay. There may also be MAXDELAY violation of around 1.6ns on this net." or "As some of the pins of the SPARTAN-3E STARTER KIT not followed the above rule, we modified the rtl generated out of mig to suit the Starter Kit hardware." I am not an expert, I am starter, but all of this does not sound good or professional at all - it tells me that there is something wrong with the memory design of the board.
he next surprise is that one has to execute a batch file first in order to be able to assemble an ISE project from all the files. I did this and found out that this project CANNOT be compiled because it needs the non-free ChipScope Pro! No docs say that I need ChipScope Pro for that board. The testbench is also not a normal one, but a strange synthesizable testbench - I don't think this is something for starters but I think I am not going to waste my time further with that. There are also some simulation exe files in a folder but they are not for the Xilinx ISim but for MentorGraphics ModelSim. I don't ask why.
I just wanted to see if I can compile the project somehow. Finally at the end of a textfile (readme.txt in the par folder) I found the hint that some files need to be modified in order to deactivate ChipScope. Unfortunately it does not seem to completely remove all the ChipScope stuff, because it is spread throughout the code. Nevertheless, I tried this option and could finally compile the code.
As I expected, there were tons of warnings including: "This constraint/property is not supported by the current software release and will be ignored.", "This is not good design practice.", gated clocks warnings, "Your design did not meet timing.", excessive clock skew, etc, etc.

Sorry Xilinx, but this is not anything I want to rely on. So my simple question to Xilinx is: Are you able to provide a working memory controller (I use VHDL) for that board which works out of the box without external clocking and hopefully with some understandable testbench for simply reading and writing to memory (it does not need to be at top speed)?

 

Best regards,

Anguel

Message Edited by alphalas on 02-16-2010 01:40 AM
9,640 Views
Registered: ‎07-03-2009

Re: Tcl error when running MIG in a newly-created project

Anguel, 

 

I'm the original poster that started this thread, and you've summarized my frustrations exactly. As someone experienced with digital electronics but not with FPGAs, I bought the Xilinx starter kit specifically because I thought it would make it easy to use the on-board DDR memory. Instead it was a buggy, complicated mess, as you've described. In my case, I eventually gave up, sold the starter kit, and abandoned the project I was working on. Not a good introduction to the world of FPGAs. 

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Historian
Historian
9,636 Views
Registered: ‎02-25-2008

Re: Tcl error when running MIG in a newly-created project

The lesson to take away from all of this:

 

Do NOT depend on ANY of Xilinx' IP. For ANYTHING.

----------------------------Yes, I do this for a living.
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Visitor alphalas
Visitor
9,633 Views
Registered: ‎12-22-2009

Re: Tcl error when running MIG in a newly-created project

Hello again,

 

I am happy that you support my post. Unfortunately it is true that the big companies don't care that small customers like us have serious problems with their products. I made a very similar experience with National Instruments - I am still waiting for an important bug fix for LabVIEW which will probably never appear because it requires a major rewrite of some core components, but that's another story...

What I want to say is that big companies can afford such things. There are not many alternatives from other companies or the alternatives have other disadvantages. Actually the Xilinx FPGAs seem to be really good, but what is an FPGA without working IP? The big companies continue to sell buggy products for years because there are enough other small users who will still buy these products and until they realize that they don't work as advertised time passes and it is impossible to return the products. By putting simple disclaimers stating that everything is provided "as is" and there is no guarantee that anything will work at all, everything is fine. This is especially true for software and development boards. By putting big company names in front of the product name and making some nice Powerpoint presentations telling how perfect everything is (please refer to the MIG videos if you don't believe me), big companies make us believe that their engineers are among the best. This is not true at all. Such products are made by engineers who don't have enough experience or don't do their job right. But why should they if noone in the company really cares that customers like me and you have problems. What chances do we have as small users to get real support? In the forums we can hope that there is some other smart user who will correct or rewrite the code for free and make it work instead of the company who sells the product. There is no hope that there will be an official fix for our MIG problem also because the Spartan 3E board is a mature product and the Spartan-6 is out. Just look at the Xilinx web site - they are only talking about the Spartan-6. At best, I expect an answer like: Buy the new Spartan-6, it has a hard memory controller. Now I know why it has a hard memory controller but I also expect that it certainly has many other bugs because it is a new product.

I came to the conclusion that the good engineers are actually at the smaller companies who are the only who really care about their products.

So what alternatives do we have as small users without much FPGA experience? Opencores.org is a good alternative but there are other problems to expect if the designer does not have enough experience. And to pay a lot of money for professional 3rd party IP just to see if it works is not an option. An finally - hey - we are talking about a standard memory controller for one of the best-selling Xilinx boards. It's a shame that there is still no solution for that.

 

Best regards,

Anguel

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