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whitehorsesoft
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Registered: ‎07-30-2020

Timer primitives or guidelines

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Newbie question: I frequently find myself trying to wait for a certain number of cycles once a condition is met, before changing state to the next condition.

The number of cycles waited varies, but can be as little as a few (wait after driving FIFO reset low), to many (send value out at the equivalent of 9600 baud on a 100MHz clocked region).

I've approached this by adding sprinklings of 'counter' variables in code, something like this:

if (cntRst < cntRstMax) cntRst <= cntRst + 1; // wait
else begin cntRst <= 0; // wait ended

 

I'm wondering, is there a 7-series primitive or a better/more efficient way to approach this problem, or conserve resources? Reading UG953 doesn't cause anything to stick out.

FWIW I am defining these variables as tightly as I can for each situation; for instance in the example above, `cntRst` would be logic[2:0] (or std_logic array if prefer in VHDL) rather than just integer or something.

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drjohnsmith
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Registered: ‎07-09-2009
which language you coding in ?

if VHDL, the idea would be to make a counter / timer component, and instantiate that where needed.

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drjohnsmith
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Registered: ‎07-09-2009
which language you coding in ?

if VHDL, the idea would be to make a counter / timer component, and instantiate that where needed.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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whitehorsesoft
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Registered: ‎07-30-2020

I'm actually bouncing back and forth between VHDL and Verilog. And system verilog. I know that's a little wacky and not a direct answer, but maybe best explained by saying "self education."

Appreciate the suggestion for making the counter/timer it's own component, seems obvious now that you've said it but I haven't considered that.

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whitehorsesoft
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Registered: ‎07-30-2020

I'm also wondering if a SLICEM shift register might accomplish this? From UG474, ch 2 under Shift Registers:

A SLICEM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can delay serial data from 1 to 32 clock cycles.

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drjohnsmith
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Registered: ‎07-09-2009
If your looking for real small counters etc using the SRL,
then the person to look for is the inventor of them, Ken chapman

https://www.xilinx.com/support/documentation/application_notes/xapp223.pdf

Again, if you make it as a component, then you can try different implementation styles , in different components,



Also try looking for his micro blaze,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>