10-20-2019 12:01 PM
I programed my project in hls and exported the ip to vivado and designed the block diagram. but when I ran the impementation, I got a timing error " [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations".
During the c systhesis also i couldnt meet the target timing. My target timing was 5.4ns and it estimated 5.6ns. I have no idea why I got this timing error in vivado design. I want to know if it is related to the timing estimation I got during the c systhesis in vivado_hls. Also I have attached a screenshot of the timing summary I got. Please help me to figure out the reason for this error/warning.
10-20-2019 12:18 PM
Without seeing the detailed report, it's impossible to give good advice, but if all of your timing failures are in the same general area, try adding some pipeline registers.
10-21-2019 10:18 AM
hey, thanks for the reply. Is there a chance that this design will work fine on the fpga board? or will it fail definetely.
Thanks in advance!
10-21-2019 10:31 AM
With more than 300 failing endpoints and failing by about 10% of a clock cycle, I would guess probably not. Or it might work on some boards and not others, or it might work until it gets warm, or it might run and give bad data. It's a safe bet that it will hang up when you demonstrate it to your boss/professor.
10-21-2019 10:33 AM