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Contributor
Contributor
16,843 Views
Registered: ‎01-07-2014

Top module setting lost

I observe the following project database corruption by Vivado (2014.2, win7 x64).

Every time I open the project in Vivado, I get  "Invalid Top module" dialog showing up.

 

 Top module 'cwtop' is currently invalid in sim_1. What would you like to do?

 

I dutyfully fill the only choice found and the project opens. This is a nuisance but it is not that bad.

 

The real problem comes if I open the project with synth/implementation results ready.

The implementation run is out-of-date. I can force it up-to-date but when I try to open the

implemented design, I get the following message:

 

ERROR: [Project 1-9] Cannot open structural netlist because no structural source files were specified. Edif, ngc ngo and verilog structural netlists are supported.
 
Now, this is CATASTROPHIC!!!
It means I cannot keep my results inside a project any longer. I have to rerun implementation (40min!!!)
every time the project is reopened!
 
Any idea where the top level definition is lost inside project database?
 
 
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9 Replies
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Xilinx Employee
Xilinx Employee
16,835 Views
Registered: ‎09-20-2012

Re: Top module setting lost

Hi,

Is this RTL or post synthesis project?

Are the project files located on local disk?

Can you try opening _routed.dcp located in .runs-->impl_1 location and see if that opens once you see the error.

Thanks,
Deepika
Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
16,821 Views
Registered: ‎07-31-2012

Re: Top module setting lost

Hi,

 

Move the design directory to the desktop or any path where the design path name is small and try. Sometimes due to the long path name, the design file might not get added.

 

You can also check the property of that top module (in the property window)after adding to make sure, it is valid for both implementation and simulation.

 

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
16,817 Views
Registered: ‎09-20-2012

Re: Top module setting lost

Just to add,

 

See if the top module name specified in the project settings matches with that of the top module.

 

This kind of issue was reported earlier when the "top module name" in the project settings was in capital letters but in the RTL it was in small letters.

 

Untitled.png

 

Thanks,

Deepika.

Thanks,
Deepika.
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Highlighted
Contributor
Contributor
16,800 Views
Registered: ‎01-07-2014

Re: Top module setting lost

Deepika,

 

 

  All my modules names are in smallcaps everywhere, there shouldn't be any problems here. 

Project is on local disk and hierarchy is not that long, just one level before project root.

 

Opening routed dcp seems to work:

 

open cwtop_routed.dcp
file4cf4300

 

Now, what can I do with it? What is the way to restore impl run results?

 

Thank you for help,

Dmitriy

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Xilinx Employee
Xilinx Employee
16,623 Views
Registered: ‎09-20-2012

Re: Top module setting lost

Hi @dmgusev 

 

We recently saw similar issue when using incremental flow. Are you using incremental flow?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Highlighted
Contributor
Contributor
16,614 Views
Registered: ‎01-07-2014

Re: Top module setting lost

Yes, I saw this problem while using incremental flow. Any ideas on fixes available?

Thx

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Xilinx Employee
Xilinx Employee
16,605 Views
Registered: ‎09-20-2012

Re: Top module setting lost

Hi,

Ok, so looks like the similar issue.

The issue which I mentioned about will be fixed in 2014.3. 2014.3 is scheduled for release in 2nd week of october.

Thanks,
Deepika.
Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
16,448 Views
Registered: ‎09-20-2012

Re: Top module setting lost

Hi @dmgusev 

 

Vivado 2014.3 has been released today.

 

Please check this issue in Vivado 2014.3 and let me know if you still see the problem.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Contributor
Contributor
12,273 Views
Registered: ‎02-20-2014

Re: Top module setting lost

Unfortunately, i met the same problem with vivado2015.4.1, i run my project on our server(ubuntu14.04.2), when i tried to archive the project, copyed to my local machine(win7,64bit) and tested with xilinx debug tool, the moment i opened the project, it's reported invaild top module,

[Common 17-9] Error reading message records

and even i found the top file(*.sv) in the project directory, i cannot assign it as top, also i cannot import the source file directory to the project, only constrains(*.xdc files) are listed in Project Manager -> Source -> Hierarchy,   actaully, when i closed and reopen the project in my server(ubuntu 14.04.2), the same problem came out.

any idea about this issue?

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