08-27-2014 06:21 PM
I observe the following project database corruption by Vivado (2014.2, win7 x64).
Every time I open the project in Vivado, I get "Invalid Top module" dialog showing up.
Top module 'cwtop' is currently invalid in sim_1. What would you like to do?
I dutyfully fill the only choice found and the project opens. This is a nuisance but it is not that bad.
The real problem comes if I open the project with synth/implementation results ready.
The implementation run is out-of-date. I can force it up-to-date but when I try to open the
implemented design, I get the following message:
08-27-2014 07:52 PM
08-27-2014 10:56 PM
Move the design directory to the desktop or any path where the design path name is small and try. Sometimes due to the long path name, the design file might not get added.
You can also check the property of that top module (in the property window)after adding to make sure, it is valid for both implementation and simulation.
08-27-2014 11:12 PM - edited 08-27-2014 11:13 PM
Just to add,
See if the top module name specified in the project settings matches with that of the top module.
This kind of issue was reported earlier when the "top module name" in the project settings was in capital letters but in the RTL it was in small letters.
08-28-2014 03:24 AM
All my modules names are in smallcaps everywhere, there shouldn't be any problems here.
Project is on local disk and hierarchy is not that long, just one level before project root.
Opening routed dcp seems to work:
Now, what can I do with it? What is the way to restore impl run results?
Thank you for help,
09-24-2014 08:20 AM
We recently saw similar issue when using incremental flow. Are you using incremental flow?
09-24-2014 06:25 PM
10-07-2014 11:24 PM
Vivado 2014.3 has been released today.
Please check this issue in Vivado 2014.3 and let me know if you still see the problem.
03-02-2016 11:45 PM
Unfortunately, i met the same problem with vivado2015.4.1, i run my project on our server(ubuntu14.04.2), when i tried to archive the project, copyed to my local machine(win7,64bit) and tested with xilinx debug tool, the moment i opened the project, it's reported invaild top module,
[Common 17-9] Error reading message records
and even i found the top file(*.sv) in the project directory, i cannot assign it as top, also i cannot import the source file directory to the project, only constrains(*.xdc files) are listed in Project Manager -> Source -> Hierarchy, actaully, when i closed and reopen the project in my server(ubuntu 14.04.2), the same problem came out.
any idea about this issue?