Design Entry

[jameson.collins]

When you make a block diagram like the one below the address map for the IC will only show IP_1 and not REGISTER_1

AXI_IC -> REGISTER_1 -> IP_1

When you make a block diagram like the one below the address map for the IC will show MY_TRANSPARENT_IP_1 as a slave device of the IC, and IP_1 as a slave device of MY_TRANSPARENT_IP

AXI_IC -> MY_TRANSPARENT_IP_1 -> IP_1

Is there anywhere to make my device transparent like the AXI register slice is?  

[muzaffer]

@jameson.collins it seems you meant to attach some images here which didn't make it.

The reason register slices are transparent is because they don't have any functionality to assign a target address. If you want to make just a monitor which monitors and passes the transactions without changing them, just make your IP and not assign any address ranges to it. I believe you should be able to package such an IP in IP creator.

[jameson.collins]

My IP, just like the register block, has no functionality to assign a target address to.  It's simply used to intercept and override certain bits in the axi transaction.

As far as I can tell the register block accomplishes this using the BRIDGES property which is assigned in a bd.tcl script.  I tried to replicate this behavior but I couldn't seem to get it to work.... I'm not even certain by bd.tcl file even runs when the block is added.