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Participant
Participant
926 Views
Registered: ‎01-11-2015

Tristate buffers in Board Design

For a recent design, placing tri-state buffer  code in the top_level_wrapper was necessary for the design to successfully work.

However, placing the tri-state buffers in Board .BD design did NOT work. I kept getting the errors about VHDL not being able to do this, but the RTL block was in Verilog and packaged as custom IP.

Reading through other threads these seems to have been identified before, but still exists in 2019.1+

Just wondering if others experienced the same.

Regards, James

 

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Teacher
Teacher
917 Views
Registered: ‎07-09-2009

you had better post all your code as an attachment

Are you intending to mix vhdl and verilog.

what board and cource you following,

Why do you say you had to have tri state buffers previously ?

Tri states are only on the IO pins of the fpga,
signals inside the FPGA can not be tri state,


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Participant
Participant
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Registered: ‎01-11-2015

This design was not intended to mix verilog and vhdl. The tri-state design was always in Verilog.

The original snippet illustrates the point, where the tristate buffers were placed in the BD design wrapper, and the design compiled successfully.

However, the same code when placed as an wrapped IP module in BD design doesn't work.

It seems BD design cannot handle tri-state assignment inside of it.

What I would be looking for is a specific example of tri-state in BD design.

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Participant
Participant
890 Views
Registered: ‎01-11-2015

Specifically, the Top Level Verilog wrapper to the BD design is where I have to place the tri-states for them to work.

If the BD design file is "design_1.bd"

Then I have to place the tri-states in "design_1_wrapper.v"

 

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Advisor
Advisor
878 Views
Registered: ‎02-12-2013

I took a look in Vivado Block Diagram Editor and I could not even see elements in the library that could be used to create a tri-state pin inside the block diagram. I know anything I have used in there just supplies the "tri" control pin along with the input and outputs. So I guess you are right you have to put the tri-state buffers outside the block diagram.
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DSP in hardware and software
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Participant
Participant
877 Views
Registered: ‎01-11-2015

Yes, and since there are no tri-state elements in teh IP menu, I wrapped Verilog using "create your own ip" and tried it that way. That did not work, either. Eventually I moved the tri-state buffers to the top level wrapper to get it to work.

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Teacher
Teacher
774 Views
Registered: ‎07-09-2009

@jbonanno1 , well found and I am taking note for the future,
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Scholar
Scholar
732 Views
Registered: ‎04-26-2012

@jbonanno1   " the same code when placed as an wrapped IP module in BD design doesn't work."

Lower level tristates and bidirectional signals don't work in Vivado IPI unless the OOC flow is disabled (select Global Synthesis in the Generate Output Products dialog box).

See the following post for more info and links:

  https://forums.xilinx.com/t5/Design-Entry/Why-does-Vivado-reject-my-bi-directional-ports/m-p/1004749/highlight/true#M21367 

-Brian

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Participant
Participant
703 Views
Registered: ‎01-11-2015

Brian, Thanks for the link on this and that additional information is quite helpful.

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