09-21-2019 07:16 AM
For a recent design, placing tri-state buffer code in the top_level_wrapper was necessary for the design to successfully work.
However, placing the tri-state buffers in Board .BD design did NOT work. I kept getting the errors about VHDL not being able to do this, but the RTL block was in Verilog and packaged as custom IP.
Reading through other threads these seems to have been identified before, but still exists in 2019.1+
Just wondering if others experienced the same.
09-21-2019 08:41 AM
09-21-2019 12:42 PM
This design was not intended to mix verilog and vhdl. The tri-state design was always in Verilog.
The original snippet illustrates the point, where the tristate buffers were placed in the BD design wrapper, and the design compiled successfully.
However, the same code when placed as an wrapped IP module in BD design doesn't work.
It seems BD design cannot handle tri-state assignment inside of it.
What I would be looking for is a specific example of tri-state in BD design.
09-21-2019 12:46 PM
Specifically, the Top Level Verilog wrapper to the BD design is where I have to place the tri-states for them to work.
If the BD design file is "design_1.bd"
Then I have to place the tri-states in "design_1_wrapper.v"
09-21-2019 01:16 PM
09-21-2019 01:18 PM
Yes, and since there are no tri-state elements in teh IP menu, I wrapped Verilog using "create your own ip" and tried it that way. That did not work, either. Eventually I moved the tri-state buffers to the top level wrapper to get it to work.
09-22-2019 04:46 AM
09-22-2019 05:00 PM
@jbonanno1 " the same code when placed as an wrapped IP module in BD design doesn't work."
Lower level tristates and bidirectional signals don't work in Vivado IPI unless the OOC flow is disabled (select Global Synthesis in the Generate Output Products dialog box).
See the following post for more info and links: