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Observer goli12
Observer
756 Views
Registered: ‎08-07-2017

Trouble adding a VHDL to a block design in Vivado 2018.1

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Hi all,

 

I have successfully tested my AES encryption core on a Pynq-Z1 using the 125 MHz clock located on pin H16. My next step is to use a PLL in the PS to test the core in the PL with higher clock frequencies.

 

However, it seems I am not able to add the module to the block diagram as it says that the RTL is an incompatible module. I have also tried Add module to block design,  but that option is greyed-out.

 

The source code including the Vivado 2018.1 project can be found here.

 

I appreciate any help :)

Cheers

goli12

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Observer goli12
Observer
729 Views
Registered: ‎08-07-2017

Re: Trouble adding a VHDL to a block design in Vivado 2018.1

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Hi all,

 

I have solved my problem. Looks like Vivado requires you to export your project into another project and create a new block design where your RTL can be imported.

 

More info can be found here: https://forum.digilentinc.com/topic/16212-adding-vhdl-code-to-block-diagram/#comment-39213

 

Regards

Andrew

 

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Explorer
Explorer
697 Views
Registered: ‎07-14-2014

Re: Trouble adding a VHDL to a block design in Vivado 2018.1

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Hi,

 

Never added RTL to the block diagram myself so I may be barking up the wrong tree entirely here, but from the first glance at your code, could it be something to with user-defined types as ports? I think Vivado has had issues with using records as ports before, but I seem to remember that the block diagrams don't deal with user defined types very well (of course that might just be my brain making stuff up! )

 

Just a thought. Might want to see if anyone else weighs in with anything else before changing all of your code.

 

Regards

 

Simon

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Observer goli12
Observer
730 Views
Registered: ‎08-07-2017

Re: Trouble adding a VHDL to a block design in Vivado 2018.1

Jump to solution

Hi all,

 

I have solved my problem. Looks like Vivado requires you to export your project into another project and create a new block design where your RTL can be imported.

 

More info can be found here: https://forum.digilentinc.com/topic/16212-adding-vhdl-code-to-block-diagram/#comment-39213

 

Regards

Andrew

 

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