UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Scholar ronnywebers
Scholar
7,857 Views
Registered: ‎10-10-2014

Tutorial on using multiple (sub) block designs in a single project

Is there any tutorial available that shows how to split up a design into multiple (sub) block designs, and combining these into a single toplevel (bd) design?

 

I've read that hardware-handoff would not work properly in this case, has this been solved yet in Vivado 2015.2?

 

I've been experimenting, but parameter propagation, address mapping, ... behaved strange, so I gave up. However it would make design reuse much more practical, and toplevel designs more manageable.

 

 

 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
1 Reply
Moderator
Moderator
7,854 Views
Registered: ‎06-24-2015

Re: Tutorial on using multiple (sub) block designs in a single project

Hi,

Check this link:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug994-vivado-ip-subsystems.pdf

 

Thanks,

Nupur

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).