UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mailavj
Visitor
4,141 Views
Registered: ‎04-10-2009

UCF Entry

Hi All

 

I am working on a design based on Virtex 5.

Right now i am in constraint locking stage. I would like to know if there is any way i can do pin locking more  easier from schematics other than assigning and typing them one by one

 

Thanks

Aravind

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
4,138 Views
Registered: ‎08-13-2007

Re: UCF Entry

I don't use schematics, but assume you are still entering your pin assignments in a ucf file instead of the schematic...

There are multiple options including Floorplanner, PACE, and PlanAhead. I would recommend the latter. If you are using ISE 10.1, PlanAhead Lite is included.

 

http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p38_41_65_FPGA101.pdf (Solving FPGA I/O Pin Assignment Challenges)

Cheers,

bt

0 Kudos