UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
345 Views
Registered: ‎07-27-2017

UCF definition for inout of type array of std_logic_vector

I have a custom datatype of t_ChioArray which is defined as "type t_ChioArray is array(natural range <>) of std_logic_vector(13 downto 0);". My top-level has an inout port defined with t_ChioArray like "CH_IO : inout t_ChioArray(NoChio-1 downto 0);"

How should I define them in the UCF file for my project using a Spartan 6 FPGA? 

NET "CH_IO[0][13]" LOC = K17 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = SLOW; kind of constraint definition is producing errors.

 

Thanks in advance!

 

0 Kudos
7 Replies
321 Views
Registered: ‎01-22-2015

Re: UCF definition for inout of type array of std_logic_vector

@amkichu 

Try defining the custom type in a VHDL package file as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- package my_pkg_file is type t_ChioArray is array(natural range <>) of std_logic_vector(13 downto 0); end my_pkg_file; -- package body my_pkg_file is --empty end my_pkg_file;


Then, in the top-level component of your VHDL project, add the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.my_pkg_file.all;

If these suggestions don't solve the problem then please show us the error you are seeing.


Mark

 

 

0 Kudos
Scholar drjohnsmith
Scholar
314 Views
Registered: ‎07-09-2009

Re: UCF definition for inout of type array of std_logic_vector

does ISE support arrays of SLV at top level ?

I have not used it for ages, but I seem to rember it was limited to std_logic and std_logic_vecotor at the pin level.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Contributor
Contributor
304 Views
Registered: ‎07-27-2017

Re: UCF definition for inout of type array of std_logic_vector

I am using such a package. One set of error is given below.

UCF line #161: NET "CH_IO[7][13]" LOC = U16 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = SLOW;

WARNING:ConstraintSystem - A target design object for the Locate constraint
  '<NET "CH_IO[7][13]"        LOC = U16   |>
  [/home/karthikselvan/Projects/intero_hdl/hdl/ldut_fpga_top.ucf(161)]' could
  not be found and so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33  |>
  [/home/karthikselvan/Projects/intero_hdl/hdl/ldut_fpga_top.ucf(161)]: NET
  "CH_IO[7][13]" not found.  Please verify that:
  1. The specified design element actually exists in the original design.
  2. The specified object is spelled correctly in the constraint source file.

0 Kudos
Scholar drjohnsmith
Scholar
294 Views
Registered: ‎07-09-2009

Re: UCF definition for inout of type array of std_logic_vector

One thought,

 

have you simulated ?

   if those pins get removed fomr the code due to an error, then you will also get this problem.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
275 Views
Registered: ‎01-22-2015

Re: UCF definition for inout of type array of std_logic_vector

@amkichu 

Using ISE v14.7 and your VHDL, I get the same warnings as you do.

I then simplified things, using the following in the VHDL package file:

type t_ChioArray is array (1 downto 0) of std_logic_vector(1 downto 0);

I also used the “out” port type instead of “inout” in the top-level VHDL component as follows:

CH_IO : out t_ChioArray;

Again, I get the same warnings.  So, the warnings are not because of the “inout” port type.

It seems that drjohnsmith is right, ISE has trouble with arrays of std_logic_vector as a port type in the top-level VHDL component.   

Mark

Contributor
Contributor
250 Views
Registered: ‎07-27-2017

Re: UCF definition for inout of type array of std_logic_vector

I tried simulation in vivado simulator (with an Artix-7 project only for easy simulation) and tried to synthesize in ISE (Spartan-6 used in our product).

I could see simulation and synthesize work good in Vivado, so couldn't notice the issue early.
0 Kudos
Xilinx Employee
Xilinx Employee
226 Views
Registered: ‎07-16-2008

Re: UCF definition for inout of type array of std_logic_vector

Did you take a look at the post-synthesis technology schematic? What is the inout port format like in the netlist?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos