08-19-2019 11:45 PM
I have a custom datatype of t_ChioArray which is defined as "type t_ChioArray is array(natural range <>) of std_logic_vector(13 downto 0);". My top-level has an inout port defined with t_ChioArray like "CH_IO : inout t_ChioArray(NoChio-1 downto 0);"
How should I define them in the UCF file for my project using a Spartan 6 FPGA?
NET "CH_IO" LOC = K17 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = SLOW; kind of constraint definition is producing errors.
Thanks in advance!
08-20-2019 05:00 AM
Try defining the custom type in a VHDL package file as follows:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
-- package my_pkg_file is type t_ChioArray is array(natural range <>) of std_logic_vector(13 downto 0); end my_pkg_file; -- package body my_pkg_file is --empty end my_pkg_file;
Then, in the top-level component of your VHDL project, add the following:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.my_pkg_file.all;
If these suggestions don't solve the problem then please show us the error you are seeing.
08-20-2019 05:44 AM
does ISE support arrays of SLV at top level ?
I have not used it for ages, but I seem to rember it was limited to std_logic and std_logic_vecotor at the pin level.
08-20-2019 07:41 AM
I am using such a package. One set of error is given below.
UCF line #161: NET "CH_IO" LOC = U16 | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = SLOW;
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "CH_IO" LOC = U16 |>
not be found and so the Locate constraint will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 |>
"CH_IO" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
08-20-2019 10:36 AM
have you simulated ?
if those pins get removed fomr the code due to an error, then you will also get this problem.
08-20-2019 04:47 PM
Using ISE v14.7 and your VHDL, I get the same warnings as you do.
I then simplified things, using the following in the VHDL package file:
type t_ChioArray is array (1 downto 0) of std_logic_vector(1 downto 0);
I also used the “out” port type instead of “inout” in the top-level VHDL component as follows:
CH_IO : out t_ChioArray;
Again, I get the same warnings. So, the warnings are not because of the “inout” port type.
It seems that drjohnsmith is right, ISE has trouble with arrays of std_logic_vector as a port type in the top-level VHDL component.
08-21-2019 12:03 AM
08-21-2019 06:07 PM
Did you take a look at the post-synthesis technology schematic? What is the inout port format like in the netlist?