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Visitor
Visitor
1,111 Views
Registered: ‎09-30-2019

Unable to export hardware from Vivado 2018.3 to SDK

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Hello,

   I created an AXI-4 master and slave streaming IP. Connected it to Zynq IP and AXI - DMA using a block diagram. I managed to generate the bitstream file. But I am unable to export the hardware. On trying to export hardware, I am getting the following error: "Cannot write hardware definition file as there are no generated IPI blocks". I want to launch SDK and write driver C code. Please let me know how to solve this issue. I have attached the archive.

Regards

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Moderator
Moderator
1,061 Views
Registered: ‎03-25-2019

Hi @mdeepakm,

Please create HDL wrapper and Generate the Output Products for your design before trying to export the HDF file:

wrapper.png

output.png

Best regards,
Abdallah
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3 Replies
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Moderator
Moderator
1,062 Views
Registered: ‎03-25-2019

Hi @mdeepakm,

Please create HDL wrapper and Generate the Output Products for your design before trying to export the HDF file:

wrapper.png

output.png

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

Highlighted
Visitor
Visitor
1,033 Views
Registered: ‎09-30-2019

Hello,

    Thanks a lot for the reply. That helped. But now I face a different issue. On trying to export the hardware with bitstream, I get the following message:

The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export. 2. There are no block design hardware handoff files. Check the vivado log messages for more details

Capture1.PNG

 

To solve it, I tried the TCL commands given here

write_hwdef -force -file C:/Users/deepa/ip_repo/edit_test2_v1_0.runs/synth_1/design_1.hwdef

write_sysdef -force -hwdef C:/Users/deepa/ip_repo/edit_test2_v1_0.runs/synth_1/design_1.hwdef -bitfile ./$PROJECT_NAME.runs/impl_1/$TOPLEVEL_NAME.bit -file C:/Users/deepa/ip_repo/edit_test2_v1_0.runs/impl_1/design_1.sysdef

But looks like no HWDEF file is created. 

Regards

 

 

 

 

 

 

 

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Highlighted
Visitor
Visitor
1,011 Views
Registered: ‎09-30-2019

Hi,

    I created the project in the Xilinx installation folder and set the design_1 wrapper.v file as top and then generated the bitstream. After this step, I am able to export it to SDK.

 

Regards

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