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Observer jluisgt
Observer
9,113 Views
Registered: ‎10-22-2014

Undesirable behavior of the IP Packager

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Hi all,

 

Am developing an IP with some VHDL files. Since am using the fixed_pkg library and have not been able to simulate it in Vivado (although it sinthesized perfectly) am adding VHDL entities gradually and left disabled the files that are not needed at some stage. The IP can synthetize and implemented, but when I package it and then reopen it with "Edit in IP Packager" the disabled files are not shown. They are in the src directory of the project but they are not shown in the Sources Pane.

 

Any idea of how to change this behavior?

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
16,403 Views
Registered: ‎09-20-2012

Re: Undesirable behavior of the IP Packager

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Hi,

You can manually add the missing files in the "file groups" section of ip packager project.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
2 Replies
Xilinx Employee
Xilinx Employee
16,404 Views
Registered: ‎09-20-2012

Re: Undesirable behavior of the IP Packager

Jump to solution
Hi,

You can manually add the missing files in the "file groups" section of ip packager project.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Observer jluisgt
Observer
9,104 Views
Registered: ‎10-22-2014

Re: Undesirable behavior of the IP Packager

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Wonderful! Thanks a lot!

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