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Adventurer
Adventurer
7,783 Views
Registered: ‎02-09-2011

Unexpected addresses for axi dma scatter gather block interface

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Hello.

 

I have a Zynq design which has an AXI DMA scatter gather interface hooked up as follows:

  The AXI DMA's M_AXI_SG block interface is connected to an AXI Interface's S00_AXI block interface. 

  The AXI Interface's M00_AXI block interface is connected to the Zynq Processing System 7's S_AXI_GP0 block interface.

 

I have the AXI DMA's GP0_DDR_LOWOCM at 0x0000_0000, size 1G.

 

There are three other addresses under the Data_SG  that I have no idea how to fill in, as I have no idea what they are:

   GP0_IOP

   GP0_M_AXI_GP0

   GP0_M_AXI_GP1

 

Could someone point me to a description of these so I can find out how to fill them in?

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
14,526 Views
Registered: ‎08-02-2011

Re: Unexpected addresses for axi dma scatter gather block interface

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Check out the 'System Addresses' table 4-1 in the zynq TRM. The S_AXI_GP* ports fall under the 'Other Bus Masters' column. IOP is the I/O Peripheral registers.

Is there a reason you're going through the S_GP ports instead of ACP or HP ports? The latter will have higher throughput and lower latency to DDR.
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Xilinx Employee
Xilinx Employee
14,527 Views
Registered: ‎08-02-2011

Re: Unexpected addresses for axi dma scatter gather block interface

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Check out the 'System Addresses' table 4-1 in the zynq TRM. The S_AXI_GP* ports fall under the 'Other Bus Masters' column. IOP is the I/O Peripheral registers.

Is there a reason you're going through the S_GP ports instead of ACP or HP ports? The latter will have higher throughput and lower latency to DDR.
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Adventurer
Adventurer
7,762 Views
Registered: ‎02-09-2011

Re: Unexpected addresses for axi dma scatter gather block interface

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Thanks.

 

Why would the SG master want access to the IO Peripheral Regs?  If I don't need this access, what address should I point it to?

 

I have the DMA MM-side data going to an HP port, and thought the conflict between that and the SG would slow things down.  Would using 2 HP ports be faster?  What if the GP port went to OCM?

 

Zynq is so rich, but so much to learn.

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Xilinx Employee
Xilinx Employee
7,651 Views
Registered: ‎08-02-2011

Re: Unexpected addresses for axi dma scatter gather block interface

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I have no idea why you'd want to do that. But you could if you wanted to :P.

I think you can leave it unmapped if you want.

Sure, SG interface on HP will technically use up a bit of bandwidth, but descriptor fetches would likely be relatively sparse. You'd have to really be pushing the limits of memory bandwidth before you'd notice it, I'd think.

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