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Newbie
Newbie
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Registered: ‎05-13-2021

Updating XPM memories with updatemem

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Hello, I am currently having an issue with populating BRAM modules using updatemem. I have 8 RAMB36 modules and one RAMB18 module for my 8192x38 ROM module. 

But when I run updatemem, only the first 1024 lines are populated. The rest are set as 0. I receive the critical warning: 

CRITICAL WARNING: [Memdata 28-315] The input data file has exceeded 32768 which is the maximum number of bits for a RAMB36 primitive. The updating of the BRAM init string is terminated. Please check your input data file.

I tried using the patch suggested in https://www.xilinx.com/support/answers/76441.html but I receive the same critical warning except it is now for the RAMB16 module. I am using ProtoCompiler O-2018.09-4-patch and Vivado 2018.1 to generate the base bit file and using Vivado 2020.2 to run updatemem. 

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ansarimo
Xilinx Employee
Xilinx Employee
217 Views
Registered: ‎12-04-2019

Is your XPM memory cascaded? If yes, then you will face this issue in 2020.2.

For cascaded XPM memory, this is a known issue that will get resolved in the later release of Vivado, instead of using updatemem flow you can use the MEMORY_INIT_FILE attribute to specify the .mem file which populates the memory during synthesis so you need to re-run Synthesis and PAR. 

For more details on the INIT, method refers to the following UG: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug974-vivado-ultrascale-libraries.pdf#page=151

This issue will be fixed in the next release of Vivado, apologies for the inconvenience caused.

There is already a CR in place to address this issue, Hope this helps.

 

Thanks and Regards,

Ansari Hunen

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1 Reply
ansarimo
Xilinx Employee
Xilinx Employee
218 Views
Registered: ‎12-04-2019

Is your XPM memory cascaded? If yes, then you will face this issue in 2020.2.

For cascaded XPM memory, this is a known issue that will get resolved in the later release of Vivado, instead of using updatemem flow you can use the MEMORY_INIT_FILE attribute to specify the .mem file which populates the memory during synthesis so you need to re-run Synthesis and PAR. 

For more details on the INIT, method refers to the following UG: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug974-vivado-ultrascale-libraries.pdf#page=151

This issue will be fixed in the next release of Vivado, apologies for the inconvenience caused.

There is already a CR in place to address this issue, Hope this helps.

 

Thanks and Regards,

Ansari Hunen

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Don’t forget to reply, kudo, and accept as a solution.
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