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Explorer
Explorer
12,455 Views
Registered: ‎07-24-2008

Use 3-state instead of large muxes, can anyone explain this to me?

Hi all,

 

   Xilinx recommands Use 3-state instead of large muxes, can you explain to me taking for an example?

 

Thank you.

Best Regards.

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Mentor
Mentor
12,445 Views
Registered: ‎11-29-2007

Where does Xilinx recommend that? It was my understanding that modern Xilinx FPGAs don't provide internal tri-state buffers, except at IO pads. Instead, tri-state logic is converted to normal logic (by MAP, I think). What device are you targetting?

 

 

Adrian



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Professor
Professor
12,426 Views
Registered: ‎08-14-2007

The original Virtex and Virtex E still had internal tristate buffers.  Also the related Spartan 2 and 2e series

had them.  Both are still in production.  Although newer parts don't have internal tristates, the tools

can convert them to logic.  I don't think that will help much in terms of logic usage, though.  For example

you could create a distributed mux by gating each source so that it drives zero when not active and

then OR all the sources together.  This is pretty much how the MicroBlaze and PPC buses work.  I

think the emulated TBUF behavior drives high when not enabled and then AND's the sources

together.

 

In the older devices with TBUF elements, you could build tristate muxes that used no LUTs other

than for decoding the select lines.  Since these parts were also considerably smaller in terms

of LUTs per device, this helped to fit larger designs in the device.

 

Regards,

Gabor

-- Gabor
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Visitor
Visitor
12,343 Views
Registered: ‎10-27-2010

To qszakacs and awillen. Please read http://www.xilinx.com/support/answers/9417.htm.

What are you thinking about?

 

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Mentor
Mentor
12,339 Views
Registered: ‎11-29-2007

I'm thinking that the AR you posted has those older devices in mind when recommending 3-state logic (see Gabor's post).



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Professor
Professor
12,336 Views
Registered: ‎08-14-2007

While this answer record was "updated" recently, it still makes some rather old

references to "Virtex vs. older families".  Just the answer record number itself

dates it as being from the era when even Virtex devices had internal tristates.

Check for answer records from the past 7 days and you'll see numbers

in the 38,000+ range.  If you're using a device such as original Virtex, Virtex E,

Spartan 2, or Spartan 2e with internal tristates, then by all means use them.

For newer devices, this trick will not help you to meet timing.

 

-- Gabor

-- Gabor
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Visitor
Visitor
12,331 Views
Registered: ‎10-27-2010

In "Timing closure 6.1i" (wp331) I read:

 

Use three-state buffers to replace large multiplexers.
♦ Virtex based FPGAs use dedicated AND-OR logic to implement three-state buffers.
- Exception: Spartan™-3 FPGAs.
♦ Can reduce multiplexer delays (improve performance).
♦ Will reduce LUT count (improve area, decrease number of LUTs utilized).
♦ Internal 3-state buffers driving the same line should all be in the same hierarchical level.

 

This wp update in 2008. I don't understand.

 

 

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Instructor
Instructor
12,324 Views
Registered: ‎07-21-2009

Use three-state buffers to replace large multiplexers.
♦ Virtex based FPGAs use dedicated AND-OR logic to implement three-state buffers.
- Exception: Spartan™-3 FPGAs.

What does "Virtex" (not Virtex 5 or Virtex 6) tell you?  You are showing that Gabor is correct.  Read his post.

This wp update in 2008.

This doesn't make a difference.  The update could refresh the letterhead graphics in the document.  It's the content that matters, not when the document was last 'touched'.

 

To sum up:  Gabor is correct on every point.  You are wasting your time by debating him, referring to ancient AR and WP docs which refer to device families which you wouldn't dream of using.

 

Ask yourself if internal tri-state buffers is important enough to give up all the advances made in FPGA architecture in the last 10 years -- including cost, speed, gate count, on-chip memory, arithmetic units, more flexible IO configurations, power dissipation, packaging, PLLs, DCMs, and memory controllers.  And don't forget to think about Virtex parts availability, now and in the future.

 

-- Bob Elkind

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Visitor
Visitor
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Registered: ‎10-27-2010

Xilinx have guidelines for timing closure? All what I find very old.

What you recommended read about timing closure?

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Mentor
Mentor
12,305 Views
Registered: ‎11-29-2007

The very first sentence of WP331 states:

NOTE: The material contained within this document is out
of date, but it is provided as a historical reference.

So ... why do you refer to it? It would also help if you told us what device you're using.

 

 


@bighedgehog wrote:

Xilinx have guidelines for timing closure? All what I find very old.

What you recommended read about timing closure?


 

Your question is too generic. Suggestion: why don't you describe what specific problem you have, and maybe we can help you.

 

 

Adrian



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Visitor
Visitor
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Registered: ‎10-27-2010

Thank you awillen and gszakacs!   I read this document. I wont read litle, compact Xilinx recomendation about timing closure, like wp331. Unfortunally they absence.

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Highlighted
2,083 Views
Registered: ‎04-07-2016

I also found Use 3-state instead of large muxes (7 or more inputs) on xilinx general answer record (not specific to a device)  that was created and updated in 2015. 

 

 www.xilinx.com/support/answers/63740.html

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