Is it possible for users to create Hierarchical IPs as described on page 20 of ug994 Designing IP Subsystems Using IP Integrator? I know it's possible to package a Block Design into an IP (AR# 59355) and it's even possible to propagate parameters from the top level BD to the packaged IP by packaging your own bd.tcl file with init() and propagate() methods as described in this post.
But when you package a BD, the IP becomes a black box and you can no longer adjust the child BD based on the parent BD parameters. I've studied the Xilinx provided 'axi_ethernet_v7_1' and 'axi_interconnect_v2_1' cores under Xilinx\Vivado\2017.4\data\ip\xilinx, but I can't figure out how the internal BD is made visible. Attached are some examples of Hierarchical IPs from Xilinx.
Are user created Hierarchical IPs not supported, or are there some packager commands to enable the child BD to be visible from the parent BD canvas?
This became important recently when trying to nest Block Design IPs more than one level deep. We wanted to set a property in the lowest level IP based on a clock frequency that is only known in the top-level BD. There appears to be no way to propagate that information down.
