01-30-2014 02:20 PM
This may be one of those cases where I'm asking a specific question, but there might be a better way to do it...
Basically, I am using the Block Diagram editor in Vivado 2013.4 with a Zynq-7000 design, and I want to break out the SD controller to the top level, so I can route it to physical pins.
Now, I initially created the Interface Port for SDIO (VLNV : xilinx.com:interface:sdio_rtl:1.0), which automatically inserts IOBUFs as needed into the top-level wrapper, but it also includes a lot of signals I don't care about in this case (LED control, card detect, write protect, bus power, etc.).
I see that I can override certain inputs by forcibly connecting them to a constant block (in the case of card detect and write protect), but how I can basically mark certain outputs as 'No Connects'?
Alternatively, I don't mind making a separate port for each piece of the SDIO interface, but I would need to instantiate a IOBUF at the block diagram level to properly connect to say SDIO0_DATA_0_I, _O and _T, correct? Simply making a discrete port that is an INOUT does not allow me to connect to those pins.
So in the end: what's the easiest way for me to remove / float the pins I do not care about at the block diagram level vs. manually editing the generated wrapper?
e: Also, Quartus has the notion of Virtual Pins, is there something similar in XDC/Vivado?
02-03-2014 10:30 AM
I think I am going to add another top-level wrapper so I no longer have to manually edit the generated wrapper from Vivado (which strikes me as the right thing to do).
02-03-2014 02:07 PM
12-24-2014 01:08 PM
yes, I would also like to add a tri-state buffer in the Block Diagram; why does the IP catalog not have a tri-state buffer?
do I need to create my own custom IP to do this? this is like reinventing the wheel; :-(
the only other option is like the previous person said is to create another top-level wrapper and do it there;
09-09-2015 01:30 AM
I'm starting to use vivado after the last project was completely created in ISE/planahead, now facing the same problem with the SD. Trying to customize things in vivado is a pain in the @$s, really fast if you just combine Xilinx Cores.
08-06-2016 12:26 PM
Its 2016 and Im using ver 2015
The utility buffer works great for differential signals (xbufds) when using IP Integrator.
Is there a similar ip available for tristate outputs (OBUFT)?
08-11-2016 05:16 PM
Here is my IP. This is very basic, single port. Only configuration is how tri-state is enabled. Just save it to a file iobuf.sv and package it with Vivado.
// Copyright (C) 2016 DSPIA INC. // Author: Muzaffer Kal<email@example.com>
// // IOBUF BD IP For Xilinx // module IOBUF #(TRI_ACT_LOW = 1) ( input io_out, input io_tri, output logic io_in, inout wire io_pad); assign io_in = io_pad; generate if(TRI_ACT_LOW) bufif0 u0(io_pad, in_out, io_tri); else bufif1 u0(io_pad, in_out, io_tri); endgenerate endmodule