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Explorer
Explorer
11,649 Views
Registered: ‎11-09-2013

Using IOBUFs in Block Diagram View?

This may be one of those cases where I'm asking a specific question, but there might be a better way to do it...

 

Basically, I am using the Block Diagram editor in Vivado 2013.4 with a Zynq-7000 design, and I want to break out the SD controller to the top level, so I can route it to physical pins.

 

Now, I initially created the Interface Port for SDIO (VLNV : xilinx.com:interface:sdio_rtl:1.0), which automatically inserts IOBUFs as needed into the top-level wrapper, but it also includes a lot of signals I don't care about in this case (LED control, card detect, write protect, bus power, etc.).

 

I see that I can override certain inputs by forcibly connecting them to a constant block (in the case of card detect and write protect), but how I can basically mark certain outputs as 'No Connects'?

 

Alternatively, I don't mind making a separate port for each piece of the SDIO interface, but I would need to instantiate a IOBUF at the block diagram level to properly connect to say SDIO0_DATA_0_I, _O and _T, correct? Simply making a discrete port that is an INOUT does not allow me to connect to those pins.

 

So in the end: what's the easiest way for me to remove / float the pins I do not care about at the block diagram level vs. manually editing the generated wrapper?

 

e: Also, Quartus has the notion of Virtual Pins, is there something similar in XDC/Vivado?

 

Thanks!

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8 Replies
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Explorer
Explorer
11,612 Views
Registered: ‎11-09-2013

Anyone?

 

I think I am going to add another top-level wrapper so I no longer have to manually edit the generated wrapper from Vivado (which strikes me as the right thing to do).

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Teacher
Teacher
11,605 Views
Registered: ‎03-31-2012

I am currently working on more IP blocks which can be used from the IP integrator. I should have the tri-state IOBUFs soon.
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Explorer
Explorer
11,587 Views
Registered: ‎11-09-2013

Excellent, I look forward to seeing them / using them.

 

Can you comment on 'virtual pins' and their implementation / equivalent in Vivado at all?

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Adventurer
Adventurer
10,098 Views
Registered: ‎12-10-2014

yes, I would also like to add a tri-state buffer in the Block Diagram; why does the IP catalog not have a tri-state buffer?

do I need to create my own custom IP to do this?  this is like reinventing the wheel; :-(

 

the only other option is like the previous person said is to create another top-level wrapper and do it there;

 

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Contributor
Contributor
8,542 Views
Registered: ‎11-29-2012

I'm starting to use vivado after the last project was completely created in ISE/planahead, now facing the same problem with the SD. Trying to customize things in vivado is a pain in the @$s, really fast if you just combine Xilinx Cores.

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Observer
Observer
5,680 Views
Registered: ‎02-01-2012

Its 2016 and Im using ver 2015

The utility buffer works great for differential signals (xbufds) when using IP Integrator.

Is there a similar ip available for tristate outputs (OBUFT)?

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Scholar
Scholar
5,664 Views
Registered: ‎11-09-2013

no everyone needs to make its own IP for tristate buffer.. we do it :)

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Teacher
Teacher
5,606 Views
Registered: ‎03-31-2012

Here is my IP. This is very basic, single port. Only configuration is how tri-state is enabled. Just save it to a file iobuf.sv and package it with Vivado.

 

// Copyright (C) 2016 DSPIA INC.
// Author: Muzaffer Kal<kal@dspia.com>
// // IOBUF BD IP For Xilinx // module IOBUF #(TRI_ACT_LOW = 1) ( input io_out, input io_tri, output logic io_in, inout wire io_pad); assign io_in = io_pad; generate if(TRI_ACT_LOW) bufif0 u0(io_pad, in_out, io_tri); else bufif1 u0(io_pad, in_out, io_tri); endgenerate endmodule
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