09-21-2011 04:21 PM
I'm not sure the exactly how to ask this question. But taking the root port design from UG517 as an example and following the instructions to build the command line implementation of the IP core PCIe. Can that post map result be "imported into ISE as a project and continued on from the GUI? i.e. Modify, simulate......
09-21-2011 11:03 PM
if it is a real IP core, that is "not haviong all I/Os connectd to IOB elements" then it schould be no problem.
You need some HDL instantiation code, or schematic symbol to connect the IP-block with the rest of your design.
Then the settings for the macro search paths in XST, Translate and Map should point to the IPO-cores directory, unless the files are in your project directory.
However, if the IP-core isn't created with coregen via the ISE GUI, you probably do not have an .xco file that could be added to the design tree. This is needed for automated core update and regeneration.
Have a nice synthesis
09-27-2011 06:53 AM
It's a core generated with the Xilinx Core Generator, and an Integrated Block in a Virtex 6. For example PCIe "Virtex-6 Integrated Block for PCI Expres". Admittedly I'm on a steep learning curve and I'm tripping my way through the process via Xilinx documentation.... Since the implement.bat process is via the command line, I thought there might be a method to inculde the results using the ISE GUI. But looking down the road, I want to build my application via the ISE GUI.
For example, if I use the example design (PCIe end point, from the core generator) xilinx_pcie_2_0_ep_v6.v as my top level and include the rest of the files in the example design, I'm getting confused as to how to include the core. So far my best success has been to add the core source files to the project, but wonder if I'm missing an easier method.
09-27-2011 10:27 PM
I took a lok at the UG517 document.
It seems the mentioned script is just a shortcut to provide users fast with some standardized simulation data.
As you can see, all the explanations show how to configure the core manually in Coregen.
However it is assumed, that someone working with such a core is skilled in the use of ISE and knows how to add an IP-core from coregen via the "New Source" wizard.
But if you prefer using scripts, which is a good idea in general, you still have the posibility to let ISE generate a Tcl script of the project. Where Tcl is preferable over a dos batch file anyway.
Have a nice synthesis
09-29-2011 07:36 AM
Skilled...:-)...:-(, hey I admitted to be on a steep learning curve. I've designed for decades, I'm not new to FPGAs (just a different mfgr), and have a little experience with ISE and cplds when it was in the single digits but not core gen ... I have found NOTHING in the documentation (and I've read a bunch) that is a good straight forward explanation of using an example design of a core generated IP part, using ISE 13.2 GUI. Up until your reply, I was using core gen via the Tools menu in ISE or via the icon in the Win 7 menu and pointing the generated core to the ISE project directory being used by ISE at the time.
I really do appreciate your replies, as I'm really struggling with 13.2 ISE GUI and core gen and have no where to turn to except this forum. The other issue I'm having is getting the ISE GUI to have the files in the correct order to build properly.
If I have one fault with Xilinx at this point in time, it's the documentation lags the ISE by a generation or two and many times bypasses the GUI completely.
09-29-2011 11:36 PM
sorrry if you got me wrong about the "skilled ise user".
That was adressed to the way the paper is written, and not about your personal situation.
There surely is some gap in the documentation, especially for the tutorials. But even with the documentation of a former version the majority of topics is still valid and correct.
I took a look at the ISE 12.4. Help PDF (which is identical to the help you get from within the Project navigator).
And if you go to the Core Generator Help section, about the VHDL Design Flow, it tells you to start the tool directly and such.
But the section about the ISE Design Flow right below leads you to the Topic "Working with Core Generator IP" with a detailed d escription on how to open a New Source for an IP-core
And this works for the 13.x version too.
But there's also good news.
Even when you generate a core directly with Coregen, a .xco file should be created.
This can be added to some ISE project and so all the cores you have made up to now should be manageable and updatable via the project navigator as well.
Have a nice synthesis
09-30-2011 06:55 AM - edited 09-30-2011 06:56 AM
The xco files have been there all along...but either adding them to the progect or including them as a new source is the same result, they aren't seen as part of the build process, thus it terminates with an error. I'm starting to wonder if I'm fighting some directory pointer problem that isn't set correctly. BTW I'm building the cores in the ISE project directory I'm working on. I have a folder on my D: drive Xilinx Projects so for example if I create project1, the core gen path for the core is D:/Xilinx Projects/project1/ipcore_dir
On synthesize I get an error: Core Generator generated file D:/Xilinx was not found.
10-03-2011 02:19 AM