01-09-2019 09:02 AM
I have a design that is using mixed language design entry. Part of the design requires the propagation of a number of settings. These settings are defined in a VHDL package file as the record type. I wish to include these in my system verilog files without having to do the conversion to the SV struct type manually (hence including additional SV package files). Is this possible in Vivado 2018?
01-12-2019 09:34 AM
check this out... " You can't use a VHDL package inside Verilog directly." ... https://forums.xilinx.com/t5/General-Technical-Discussion/call-vhdl-package-in-verilog/td-p/566899
Please mark as 'solution accepted' to close the issue.
01-14-2019 01:51 PM
Is this true for SV as well? I would imagine so, but if System Verilog supported that, It would be very helpful.