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Observer
Observer
1,261 Views
Registered: ‎07-31-2018

Using VHDL packages in a SystemVerilog file

Hi all, 

I have a design that is using mixed language design entry. Part of the design requires the propagation of a number of settings. These settings are defined in a VHDL package file as the record type. I wish to include these in my system verilog files without having to do the conversion to the SV struct type manually (hence including additional SV package files). Is this possible in Vivado 2018?

 

Cheers 

 

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Teacher
Teacher
1,199 Views
Registered: ‎10-23-2018

Re: Using VHDL packages in a SystemVerilog file

@lasthorizon711

check this out... " You can't use a VHDL package inside Verilog directly." ... https://forums.xilinx.com/t5/General-Technical-Discussion/call-vhdl-package-in-verilog/td-p/566899

Please mark as 'solution accepted' to close the issue.

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Explorer
Explorer
1,167 Views
Registered: ‎07-18-2018

Re: Using VHDL packages in a SystemVerilog file

Is this true for SV as well? I would imagine so, but if System Verilog supported that, It would be very helpful.

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Newbie
Newbie
241 Views
Registered: ‎05-01-2020

Re: Using VHDL packages in a SystemVerilog file

Is there any update on this? I am using 2019.1 and seeing this issue.

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