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Observer
Observer
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Registered: ‎10-17-2011

Using Vivado generated IP in ISE - is this possible?

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I have a legacy design done using ISE which needs to be upgraded.  I don't want to migrate the project to Vivado; too risky for now.

There are some cores in Vivado IP Integrator I would like to use. Is it possible to generate them in Vivado, and then use in ISE. Maybe export in a format which ISE can instantiate?

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Teacher
Teacher
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Registered: ‎07-09-2009
I'm afraid, I agree with you, that going to vivado is the better option , despite the short term pain,

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Teacher
Teacher
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Registered: ‎07-09-2009
No,

a) IP is generally encrypted, and ISE encryption does not as far as I know support the same encryption as vivado.

b) Even if the IP is not encrypted, the IP, is generally device specific, so if you make an IP for say a zynq and try to put that into say an ultrascale, then the "blocks" used in the IP may not be available, such as say the PLL is a different block between the two devices.

Like all / most software, most IP can be taken from ISE, and re compiled in vivado, but not the other way.
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Observer
Observer
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Registered: ‎10-17-2011

Thanks for the reply. If I say use a Kintex 7 device which is supported by both Vivado and ISE can I then use the Vivado IP in ISE assuming its unencrypted of course?

As part of this project I’m trying to connect an AXI-4 Stream to the UFC interface of the Aurora core. Is there a block that handles the interconnection or can I simply use the AXI-4 Stream register slice to delay the stream by 2 clocks and drive ufc_tx_req with the TVALID from the stream (the input to the register slice)?

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Teacher
Teacher
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Registered: ‎07-09-2009
I doubt its designed to work like that
The two tools have totaly different backgrounds,
vivado can import older ISE designs and upgrade them to the latest, but there are still problems, such as the timing files in ISE can not be used in vivado, so any timing constraints built into any IP you generate in one and use in the other , will have no timing constraints,

it does not mean it might work,
but as its not a supported flow,
its going to be up to you to test and prove it,

On a more fundamental level, If you have a device in vivado, why are you using ISE ?

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Observer
Observer
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Registered: ‎10-17-2011

Only reason is did original design in ISE (some years ago). We need to make some changes, so was hoping we can do this in ISE rather than try import into Vivado. If we do this, will need to go through full qualification again.  But maybe no choice.

Thanks

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Teacher
Teacher
222 Views
Registered: ‎07-09-2009
I'm afraid, I agree with you, that going to vivado is the better option , despite the short term pain,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Observer
Observer
219 Views
Registered: ‎10-17-2011

Thanks