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Utility Buffer IP overrides clock period after upgrading to Vivado 2017.4

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Participant
Posts: 38
Registered: ‎11-09-2012
Accepted Solution

Utility Buffer IP overrides clock period after upgrading to Vivado 2017.4

After upgrading Vivado from 2016.4 to 2017.4, the Utility Buffer that I am using to buffer the differential input clock (using Board > Clock Sources > System differential clock for the VC707) now adds its own constraint file and overrides the clock period as follows.

 

create_clock -period 10.000 [get_ports IBUF_OUT]

So even though the input clock is properly constrained to 200 MHz in one of my project .xdc files, the Utility Buffer overrides it to 100 MHz. This was not happening in 2016.4. In fact, the Utility Buffer did not even have a constraint file in 2016.4.

 

Why is this happing in 2017.4, and how do I work around it?


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Participant
Posts: 38
Registered: ‎11-09-2012

Re: Utility Buffer IP overrides clock period after upgrading to Vivado 2017.4

So even though I had constrained the input clock, and the MIG clock was also properly constrained by the MIG generator, somehow the Utility Buffer constraint was overriding everything. I don't know that changing the order of my constraint file would help any since it was "normal" and the Utility Buffer was already "early" by default.  I corrected the input frequency by setting the property of the top level clock input port in IP Integrator to 200MHz and validated and synthesized. Unfortunately, Vivado did not propagate this change to the Utility Buffer constraint file (even though its input port property showed 200MHz correctly). I had to delete the Utility Buffer and insert a new one before Vivado properly propagated the clock period. Once Vivado finally cooperated, the errors I was seeing due to the incorrect clock period were eliminated.

 

It really does not make sense to me that my constraint was ignored even though it was configured to be processed after the Utility Buffer IP core's constraint. This was not a problem in previous versions of Vivado. Frankly, this seems like a bug in Vivado to me.

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Xilinx Employee
Posts: 5,894
Registered: ‎08-01-2008

Re: Utility Buffer IP overrides clock period after upgrading to Vivado 2017.4

You don't change the property on the IBUF_OUT pin but you change the frequency of the I/O port connected to CLK_IN_ interface. Double click on the port to open the Customize Port dialog box. Specify the correct frequency in there and validate the design. It will validate

Thanks and Regards
Balkrishan
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Xilinx Employee
Posts: 253
Registered: ‎05-06-2008

Re: Utility Buffer IP overrides clock period after upgrading to Vivado 2017.4

Hello Brian,

 

In the project flow, you can change when the compile processing ordering of the constraints to be 'late' with the following command:

 set_property PROCESSING_ORDER LATE [get_files T:/casesK/project_bft_ex/project_bft_ex.srcs/constrs_1/imports/xcku035-fbva900-2-e/bft_full.xdc]

 

If this constraints file has the correct clock period, it will override any changes done at the IP level or previous constraints files.

 

Thanks

Chris

Highlighted
Participant
Posts: 38
Registered: ‎11-09-2012

Re: Utility Buffer IP overrides clock period after upgrading to Vivado 2017.4

So even though I had constrained the input clock, and the MIG clock was also properly constrained by the MIG generator, somehow the Utility Buffer constraint was overriding everything. I don't know that changing the order of my constraint file would help any since it was "normal" and the Utility Buffer was already "early" by default.  I corrected the input frequency by setting the property of the top level clock input port in IP Integrator to 200MHz and validated and synthesized. Unfortunately, Vivado did not propagate this change to the Utility Buffer constraint file (even though its input port property showed 200MHz correctly). I had to delete the Utility Buffer and insert a new one before Vivado properly propagated the clock period. Once Vivado finally cooperated, the errors I was seeing due to the incorrect clock period were eliminated.

 

It really does not make sense to me that my constraint was ignored even though it was configured to be processed after the Utility Buffer IP core's constraint. This was not a problem in previous versions of Vivado. Frankly, this seems like a bug in Vivado to me.