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Explorer
Explorer
1,930 Views
Registered: ‎12-21-2012

VHDL-2008/VHDL2019 support in IPI?

It is very upset to see that Vivado supports synthesis of VHDL-2008, but IPI doesn't even after 2019 standard is out. If I want to use IPI to package designs, I must not use VHDL-2008. Of course I can live without IPI at the cost of less convenience, but, does Xilinx have any plan to support 2008 or even 2019 standard in IPI, and in the whole Vivado toolset in the future? Xilinx has been blowing out high level design tools, but hardware design seems to be, to some extent, neglected.

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Teacher
Teacher
1,909 Views
Registered: ‎07-09-2009

Re: VHDL-2008/VHDL2019 support in IPI?

Experience has shown that if its VHDL, then Xilinx show very very little interest,
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Scholar
Scholar
1,898 Views
Registered: ‎08-01-2012

Re: VHDL-2008/VHDL2019 support in IPI?

Dont hold your breath. Current focus is SV and UVM in the simulator and HLS (Vitis). HLS especially opens the market open wide, as they claim you can easily port your C code. The less efficent the better as it will sell more of the larger chips.

Vivado doesnt even have 2008 support in the simulator yet. VHDL 2019 has limited support in only the newest versions of 3rd party simulators.

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Explorer
Explorer
1,838 Views
Registered: ‎06-25-2014

Re: VHDL-2008/VHDL2019 support in IPI?

I'm also very interested in this subject and would like to know what Xilinx's official long term plans are.  And, if they are only supporting System Verilog as a HDL going forward, then so be it. At least I can then make appropriate plans.

I just cannot see HLS etc. as good enough yet (or probably ever TBH) to cover all applications. (Particularly higher volume where every LUT and MHz is massively important to the customer to meet cost points)

 

And it's these high volume customers that have a BIG voice in how Xilinx approach their entire business. Xilinx are taking a risk if they are not properly supporting the main HDL languages and with a newly ratified version of VHDL announced they really should be more public on their intentions.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

VHDL-2008 (and SystemVerilog) is supported in IPI in the lower levels of hierarchy.  We cannot support it at the top level because of the dynamic nature of the ports which we can't accomodate from a connectivity point of view.  This is true in IP Packager and module reference.  Just be sure to use 2019.1+

 

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Teacher
Teacher
1,772 Views
Registered: ‎07-09-2009

Re: VHDL-2008/VHDL2019 support in IPI?

That is apart from the simulator , which has very limited 2008 support,

As for 2019, dont expect that as its mainly simulator changes
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Scholar
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1,697 Views
Registered: ‎04-26-2012

Re: VHDL-2008/VHDL2019 support in IPI?

@cdunlap   "VHDL-2008 (and SystemVerilog) is supported in IPI in the lower levels of hierarchy. <snip> This is true in IP Packager and module reference."

This statement contradicts both the current documentation[1] and previous 2018.x information posted by Xilinx[2], which state that VHDL-2008 is not allowed *AT ALL* in the IP Packager flow, and only at lower levels for the Module Reference flow.

Has the allowed use of VHDL-2008 in the IP packager been changed in 2019.x?

If so, where can I find the documentation for this change?

> We cannot support it at the top level because of the dynamic nature of the ports which we can't accomodate from a connectivity point of view.

Are there any plans/efforts underway to fix the underlying limitations and/or architectural issues with IPI that prevent it from supporting the following constructs as generics and ports ?

  - real generics (regression from ISE XPS)
  - user defined types
  - constants and functions defined in packages
  - port range expressions involving functions
  - VHDL records / SystemVerilog interfaces
  - top-down propagation of generics within an OOC flow (regression from ISE XPS platgen)

-Brian


[1] UG1118 2019.1 (Xilinx website identifies this as the latest version for 2019.2)
     https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1118-vivado-creating-packaging-custom-ip.pdf

vivado_IPI_VHDL2008_2019v2.png


[2] April 2018 post by howardp
     https://forums.xilinx.com/t5/Design-Entry/Does-IPI-support-modules-using-VHDL2008/m-p/849171/highlight/true#M16585
     "From my understanding, one still can not use *any* VHDL-2008 specific HDL in the 2018.1 IP packager flow."

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Xilinx Employee
Xilinx Employee
1,573 Views
Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

@brimdavis 

Yes I am aware of the contradiction in the UserGuide.  This will be fixed in 2020.1.  

The work to support SystemVerilog and VHDL-2008 in the lower levels of hierarchy is relatively new (2019.1).  We wanted to get some testing in before changing the docs to say it is supported.  

Supporting SystemVerilog and VHDL-2008 in the top is not in the current plan but I am trying to get this into plan for 2013.1.  It is not trivial, so no promises. But I know there is a lot of requests for this, and I will try to accomodate it.

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Teacher
Teacher
1,542 Views
Registered: ‎07-09-2009

Re: VHDL-2008/VHDL2019 support in IPI?

Well done @cdunlap on waving the flag for VHDL 2008 , its great to see some Xilinx movement on this much neglected area of Xilinx,

( seriously, we still see xilinx using clk'event instead of rising_edge , so some one standing up for VHDL 2008 is great news )
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Observer
Observer
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Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

I'm using Vivado 2019.2, and VHDL-2008 in lower levels of the IP Packager hierarchy.  The IP Packager packages the IP fine, but it won't synthesize, and Vivado won't let me set the source file properties to VHDL-2008.  Filenames changed in the following message to

[filemgmt 20-1702] Unable to set property on the file: c:/ZZZ/Designs/TestXXX/TestXXX.srcs/sources_1/bd/TestXXXIpi/ipshared/f960/src/XXXControl_Top.vhd
File is managed as part of sub-design (IP, Block Design, DSP Design, etc.) file: c:/ZZZ/Designs/TestXXX/TestXXX.srcs/sources_1/bd/TestXXXIpi/ip/TestXXXIpi_XXXControl_Axi_0_0/TestXXXIpi_XXXControl_Axi_0_0.xci

There doesn't appear to be a way to select VHDL-2008 for source files in IP Packager.  What am I missing?

 

Thanks,

Paul

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

Hard to tell for sure but it seems you have a subcore here?  In that case you don't need to tag it.  It would already be compiled through the IP flow.  I assume everything compiles fine first without the packager.  We might need to see the project to see what is going on.

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Observer
Observer
1,212 Views
Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

If I take the same exact set of source I'm packaging as IP, and build it as an independent design, specifying each file as "VHDL 2008", it compiles/synthesizes fine (is there a way to set every VHD file as 2008 by default in a project?).  There are no sub-cores, all the VHDL is our own internal proprietary code, with AXI4-Lite wrappers to package as IP.

There simply doesn't seem to be a way to tell the IP packager that my .VHD files are VHDL-2008.

I thought perhaps I could work around this by only including the top-level AXI interface VHDL in IP packager (no VHDL-2008), and adding the rest manually to the design project, where i *can* set them as VHDL 2008, .  However, Vivado is unable to resolve these files during synthesis/implementation with the IP packager entities instantiated in the Block Design ("Could not resolve non-promitive black box...", even though I've moved these files to compile before the block design.

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Teacher
Teacher
1,204 Views
Registered: ‎07-09-2009

Re: VHDL-2008/VHDL2019 support in IPI?

We have all been crying out for this , but it seems xilinx are not at speed on vhdl,
The last answer was on lines of , TCL solves everything.
I think xilinx only really use scripting modes in the office .
Mind u , they modified the forums over the weekend , so may be a bit distracted
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Observer
Observer
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Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

Even though IP packager won't let me set the file type in the UI, running this command does:

set_property FILE_TYPE {VHDL 2008} [get_files -filter {FILE_TYPE==VHDL}]

The UI reflects this change.  However, when "upgrading" the IP in my IPI design, this attribute does not get updated, it reverts to VHDL.  Running this command in my IPI design gives this error for the files packaged by IP Packager:

CRITICAL WARNING: File is managed as part of sub-design (IP, Block Design, DSP Design, etc.)

So, the bottom line:  IP Packager doesn't save source file properties (or save them in component.xml), and an IPI design won't let me set the source file properties of IP.   Is there an XML string that will set the filetype to VHDL 2008 in component.xml?

I see "fileType" tags like this:

" <spirit:fileType>vhdlSource</spirit:fileType>

-Paul

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Xilinx Employee
Xilinx Employee
1,143 Views
Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

@pkinzer There was a bug about a year and half ago where the packager dropped the VHDL-2008 parameters when it passed things to Vivado.  I think that was 2018.1 or 2018.3.  But that has been fixed.  You can't tag files after you package IP.  The flow is to have a project with all files tagged as appropriate, then run the packager.

 

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Observer
Observer
1,126 Views
Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

Thanks.

I'm using 2019.2, so shouldn't have that particular issue.  So here's my flow.  I right click my component, "Edit in IP packager".   This opens up a temporary project.  In that project, after bringing in all the VHDL files, I run "set_property FILE_TYPE {VHDL 2008} [get_files -filter {FILE_TYPE==VHDL}]", which I can see tags all the source files.  Then I "Review and Re-Package", and close that project.  In my IP Integrator Design, I click "Upgrade IP".  After the OOC module runs are done, I drill down the hierarchy in "IP Sources", and the file type is still "VHDL".

What am I missing?

-Paul

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

@pkinzer Can you just create a project with the IP you want to package.  Ensure all files are tagged as appropriate and constriants are set.  Synthesize to ensure everything works fine.  Then go to tools -> create and package new IP.  Then package the project.

Check the ip packager gui and ensure HDL file types are set properly (but they should have been set in the project before running the packager).

 

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Observer
Observer
1,067 Views
Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

OK, I ran through that scenario, with interesting results.  After clicking "Tools | Create and Package new IP", then "Next", I'm given the option to "Package your current project", or "Package a specified directory".    I've always used "Package a specified directory", more on that later.  If I select "Package your current project", it COPIES all the files to a new location, including common packages shared among multiple projects.  However, the component.xml it creates in this new folder has these tags for each VHDL file:

<spirit:userFileType>vhdlSource-2008</spirit:userFileType>

This then properly imports these as "VHDL 2008" files when the component is instantiated in an IPI design.

My flow is to use "Package a specified directory", which creates a component.xml with this tag for each VHDL file:

<spirit:fileType>vhdlSource</spirit:fileType>

This seems to be the root of the problem.  Stay tuned...

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Observer
Observer
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Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

And now, the rest of the story.  The problem with "Package your current project" is that it copies all source files to a new location.  This is flow is unusable with source control, which relies on source files being in one and only one place, so a project can be completely re-created by retrieving a minimum set of files to a new location, and the project built from scratch.  We have shared packages in a "Libraries" folder, re-usable modules in a "Blocks" folder, and multiple designs that use both.  All these locations are mapped into our source control system, so it's critical they don't get copied anywhere.  This means we must use the "Package a specified directory", as it is the only way to package the files in their original location, and create a component.xml in that location, so that it can be version controlled with the source, without any copies.  We re-create our IPI design with a TCL script, so none of the Vivado created folders (.cache, .hw, .ip_user_files, .runs, .sim, .srcs) need exist when re-creating a project from source control.

Anyhow, I found that when using "Package a specified directory", in the Packaging Step | File Groups, each file has the type set to "vhdlSource".  I changed these all to "vhdlSource-2008", and finished packaging.  When instantiating in a block design, and drilling down into IP sources, in the "Source File Properties" window, I see the type is now properly set as "VHDL 2008".  This is a functional workaround for now.  It's unclear if "vhdlSource-2008" is part of the IP-XACT standard, or a Xilinx extension.

What needs to change, is some sort of option when using "Package a specified directory", to import the files as VHDL 2008, since the TCL command "set_property FILE_TYPE {VHDL 2008} [get_files -filter {FILE_TYPE==VHDL}]" doesn't affect the packager.  Or at the very least, UG1118 updated to reflect the workaround I found.

-Paul

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: VHDL-2008/VHDL2019 support in IPI?

Source control and xilinx tools don't mix in the real world.
My bet is xilinx don't use them when testing.
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

@pkinzer The general purpose of the package current project is to create an IP block you can ship to an end user / customer.  In this mode, the source must be with the IP and that is why we do it.  If you want to package a specific directory because you are your own consumer of the packaged IP, that is fine and you have a path forward.  Setting the file type through the wizard is the standard way to do this too.  I am not sure what you mean by a gap in the user and a work around you found.  Using the packager to set the file type is what we say in UG1118.  

@drjohnsmith There have been many improvements to Vivado to support revision control (more coming in 2020.1 too).  Perhaps it would be best to start a new forum entry on revision control.  I'll admit a perfect answer is not an easy one to understand but I am happy to help clear the air on what can and cannot be done to support your revision control needs.

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Observer
Observer
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Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

@cdunlap Quoted from previous msg: " I am not sure what you mean by a gap in the user and a work around you found.  Using the packager to set the file type is what we say in UG1118."

Where in UG1118 does it say "vhdlSource-2008" can be used?  It's not in the 2019.1 version of the doc, and I can't find a newer version.  The only text in UG1118 referencing VHDL 2008 is this: "The IP packager does not support VHDL-2008" on page 11.  Searching the entire catalog in DocNav doesn't turn up any reference to the string "vhdlSource-2008".

When packaging a source directory (not an entire project), setting the Type to "VHDL 2008" in "Source File Properties" doesn't change the text in the packager from "vhdlSource" to "vhdlSource-2008".  This must be manually typed in.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Re: VHDL-2008/VHDL2019 support in IPI?

@pkinzer I answered the doc gap above and it will be addressed in 2020.1.  OK I understand your issue and will look to get it solved for 2020.2.

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Observer
Observer
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Registered: ‎10-07-2019

Re: VHDL-2008/VHDL2019 support in IPI?

Thank you.

-Paul

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Explorer
Explorer
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Registered: ‎12-21-2012

回复: VHDL-2008/VHDL2019 support in IPI?

OK, 2020.1 was out few days ago. As I checked UG994 v2020.1:

SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the top-level of the RTL module.

So my pain persists. Is IPI planned to support full support of 2008? Or maybe I should start trying to fabricate a script to convert 2008 to an earlier version?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

回复: VHDL-2008/VHDL2019 support in IPI?

@fiedel as stated above there was never a plan in 2020.1 to support VHDL-2008 in the top level.  Only the lower levels of hierarchy.  We cannot support the dynamic nature of ports that you can get with VHDL-2008 / SV so it is not possible in the top level. 

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Scholar
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Registered: ‎04-26-2012

回复: VHDL-2008/VHDL2019 support in IPI?

@cdunlap "We cannot support the dynamic nature of ports that you can get with VHDL-2008 / SV so it is not possible in the top level."

Your response in December 2019 regarding top level port support was rather different:

"Supporting SystemVerilog and VHDL-2008 in the top is not in the current plan but I am trying to get this into plan for 2013.1.(sic) It is not trivial, so no promises. But I know there is a lot of requests for this, and I will try to accomodate it."

Up-thread I'd asked you the following questions, which remain mostly unanswered:

Are there any plans/efforts underway to fix the underlying limitations and/or architectural issues with IPI that prevent it from supporting the following constructs as generics and ports ?

- real generics (regression from ISE XPS)
- user defined types
- constants and functions defined in packages
- port range expressions involving functions
- VHDL records / SystemVerilog interfaces
- top-down propagation of generics within an OOC flow (regression from ISE XPS platgen)

<editorial rant>

Frankly, the continuing inabliity (i.e. since 2012) of IPI to handle such constructs is a glaring omission, as what you have created with IPI is a low level tool being peddled as a "high level" design tool.

Similar tools from your competitors handle VHDL records as top level ports.

And why the #$@&^! does one have to deconstruct an SV interface into discrete signals in a wrapper with X_INTERFACE attributes, then slather it with XML, in order for IPI to treat it as an "interface" in the BD?

-Brian

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

回复: VHDL-2008/VHDL2019 support in IPI?

@brimdavis Yes we know this is a common request but it is a very complex thing to solve and we will get there eventually.

In 2020.1 the focus was block design container which is a new feature but an EA feature that allows embedding block designs in a block design.  You could also call this team design.  It allows multiple people to work on different block designs and to stitch them all together in one block design.  It has advantages over module reference in the sense that the interface ports are understood and connection automation is maintained. 

I can't promise when SV or VHDL-2008 at the top will be supported but we are constantly discussing this and trying to get this scheduled in an upcoming release.

 

 

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Scholar
Scholar
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Registered: ‎08-01-2012

回复: VHDL-2008/VHDL2019 support in IPI?

On a similar note, why are there IPs that are IPI only? To get these, we literally have to create a bd file purely to get a single ip. Underneath it's all hdl. It's less maintainable than the ip catalogue.

Why don't you trust your users to instantiate these ips themselves? Altera have always given users the option to manually instantiate all ips with documentation on the entire interface and parameters.  It means when we have two parts using the same design, I need 2 BDs. In altera I could just set the part via a parameter (if it didn't auto set it). It bloats the repo and needs special scripting to get everything generated.  Such a mess.

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Registered: ‎04-26-2012

回复: VHDL-2008/VHDL2019 support in IPI?

@cdunlap   "it is a very complex thing to solve and we will get there eventually"

Thanks for the clarification, I'd read your recent post as saying "can't support" vs. "support someday".

> I can't promise when SV or VHDL-2008 at the top will be supported 

Some items on my above unaddressed-list-of-IPI-ommisions, such as supporting real generics as did XPS, are plain-old-VHDL, and should be trivial to implement- I've been asking Xilinx about real generics in IPI for years with no response.

Others, such as the bottom-up-only-OOC flow in Vivado are horrible ommissions, given that XPS handled this better decades ago (top down parameter propagation that rebuilt only the changed modules).

Personally I find RTL flows much more productive than IPI, as being able to use higher level constructs like interfaces/structures/records/arrays in SV/VHDL eliminates much of the parameter/port interconnect boilerplate (i.e. instead of hundreds of config parameters for a complex IP, you have one config record, or an array of records lining up with an array of ports.)

But that said, I have to deal with IPI designs, and package stuff for other folks who use IPI, which is when the explode-design-into-plain-old-verilog-port-equivalents-wrapper + tcl-script-to-dynamically-generate-wrapper-variants + xml + X_INTERFACE stuff becomes frustrating and time consuming, especially as many of the 'advanced' features remain poorly documented 8 years after Vivado launch, and require inspecting the generated tcl/wrappers/HDL from Xilinx IPI cores to sort out how things work.

-Brian

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