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Explorer
Explorer
2,047 Views
Registered: ‎12-21-2012

VHDL-2008/VHDL2019 support in IPI?

It is very upset to see that Vivado supports synthesis of VHDL-2008, but IPI doesn't even after 2019 standard is out. If I want to use IPI to package designs, I must not use VHDL-2008. Of course I can live without IPI at the cost of less convenience, but, does Xilinx have any plan to support 2008 or even 2019 standard in IPI, and in the whole Vivado toolset in the future? Xilinx has been blowing out high level design tools, but hardware design seems to be, to some extent, neglected.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

@richardhead which IPs are you referring to that you want outside of IPI?  Some of the AXI smartconnect have a common need in IPI but not so much outside of IPI.  Very little feedback or requests to add IP like this outside of IPI.  Please describe your use case.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

@brimdavis we are working on resolving the RTL vs IPI gap.  We will get there but it will take some time. 

@brimdavis Of course the huge benefit of IPI is your ability to rapidly connect lots of IP together with connection automation.  You can also add RTL in IPI and likewise can put your IPI based BD in your RTL.  So you can leverage RTL as much as you want but get the benefits of rapid connections with IPI.

Our first major project is block design containers which will allow the insertion of a BD in a BD.

Our next major project will be parameter propagation from the top level.  This would be akin to generics at the top.

Following that will be SV / VHDL-2008 at the top.  

These are goals but as mentioned, hard to say when all these will show up.  Block design container is already there in 2020.1 as in EA feature. 

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Scholar
Scholar
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Registered: ‎08-01-2012

@cdunlap 

Particularly, the AXI Interconnect v2.1

 

interconnect.PNG

 

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Xilinx Employee
Xilinx Employee
437 Views
Registered: ‎10-01-2007

@richardhead why are you trying to use AXI interconnect in RTL?  The whole point of IPI is to reduce the burden of connecting the hundreds of AXI signals together by hand.  It would be far easier to connect them in IPI then place that BD in your RTL.

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Scholar
Scholar
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Registered: ‎08-01-2012

Because then the design doesnt play nice in version control ( can easily see the changes in an XCI - have you done a diff on a BD file? ). Plus all Masters are custom RTL, and the single endpoint is a MIG. Plus the Interconnect has different configurations depending on what variant is being built (from a single RTL set). And finally the RTL is VHDL 2008 with functions to convert the really annoying XIlinx IP interefaces to our custom types. Basically, IPI is not much use to us.

Currently we have two separate Interconnect RTL  (v1.7) .xci files depending on what we're building (with the same MIG endpoint). There are 4/5 Masters with Varying WDATA/RDATA widths (32 -> 128) with the MIG being 512.

Why shouldnt I want to use an interconnect in RTL? With the inflexability of IPI, are you surpised larger companies tend to roll their own AXI infrastructure (that usually can be used in both Xilinx and Altera).

 

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Scholar
Scholar
381 Views
Registered: ‎08-01-2012

I also contend that my RTL is cleaner and clearer than the IPI even:

signal ic_m2s_array : axi4_a32_d128_m2s_array_t(3 downto 0);
signal ic_s2m_array : axi4_a32_d128_s2m_array_t(3 downto 0);

...

device0_inst : entity lib.my_rtl1
port  map (
  -- entire axi4 connection in 2 lines
   ram_m2s => ic_m2s_array(0),
   ram_s2m => ic_s2m_array(0),
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Observer
Observer
366 Views
Registered: ‎10-07-2019

@richardhead "Because then the design doesnt play nice in version control ( can easily see the changes in an XCI - have you done a diff on a BD file?" 

While I'm not condoning the lack of VHDL-2008 support, in the case of .BD files, saving them as a TCL file (write_bd_tcl) works much better in version control, and is a straight-forward diff.  We tweak the generated tcl to remove and re-create the existing .bd file if it already exists, but otherwise use it as-is.  With this method, this Project.srcs folder is essentially a temporary folder.

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Scholar
Scholar
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Registered: ‎09-16-2009


@cdunlap wrote:

@richardhead why are you trying to use AXI interconnect in RTL?  The whole point of IPI is to reduce the burden of connecting the hundreds of AXI signals together by hand.  It would be far easier to connect them in IPI then place that BD in your RTL.


Using SystemVerilog interfaces, connecting up an AXI bus in RTL is a one liner.  

axi_if my_axi_if();
 ...
master_sub_module master_sub_module
(
   .m_axi_if( my_axi_if )
);
slave_sub_module slave_sub_module
(
    .s_axi_if( my_axi_if )
); 

100's of connection down to one line.  1000s of pointy-clicky's replaced by one line of code.  And revision control friendly.  And industry standard.  And reusable.  And not tied to any specific tool.

Which one is far-easier?

Regards,

Mark

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Scholar
Scholar
347 Views
Registered: ‎04-26-2012

@cdunlap  "Of course the huge benefit of IPI is your ability to rapidly connect lots of IP together with connection automation."  "The whole point of IPI is to reduce the burden of connecting the hundreds of AXI signals together by hand."

The automation of unnecessary boilerplate does not make it any less unnecessary...

As I mentioned up thread, and as clearly illustrated by the examples of @richardhead and @markcurry , you can do stuff like AXI plumbing much more succinctly and flexibly in RTL than with IPI.

For those of use who have to write RTL to be used within IPI, being able to use VHDL records, SV interfaces, packages, etc. directly in IPI *without* having to add all the wrappers and other superfluous ornamentation to the RTL, would make it a much better tool.

-Brian

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Xilinx Employee
Xilinx Employee
301 Views
Registered: ‎10-01-2007

We changed the BD to a JSON format in 2018.3 to help with revision control diff analysis.  We also have a utility that can compare BD files and integrate into a revision control environment.

We are also working on separating source and output products so it is easy to know what to check in for revision control.

If you check the .BD and .UI into revision control you will be able to get your diagram back up the same way you had it before.  

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