03-02-2015 07:07 AM
I have some trouble using VHDL-2008.
An attempt to follow AR#62005 fails:
CRITICAL WARNING: [filemgmt 20-1702] Unable to set property on the file: c:\[clip]/file.vhd
File is managed as part of sub-design (IP, Block Design, DSP Design, etc.) file: [clip]/design.xci
The AR does not, however, tell how declare the use of vhdl-2008 inside an IP block.
Clicking "Edit in IP packager -> Project Manager - Sources - Hierarchy - file.vhd -> Source file properties - properties", I see an option to set the file type to "VHDL 2008". That information does not seem to propagate to the xci file when repackaging the IP project. The same is true also when using the tcl command referred in the AR.
What is the correct way to tell Vivado to synthesize a certain file, wrapped inside an IP block, using VHDL-2008 compiler mode?
03-02-2015 06:27 PM
03-02-2015 10:23 PM
As far as I see, there are no options to select a file type before entering the IP editor. In the IP editor, there are some ways to choose the file type, like the one I quoted in the original question or in "Packaging steps -> File Groups -> Type". In the latter, there are many options like "vhdlSource-87, vhdlSource-93, and vhdlSource" but at least the tooltip does not explicitly mention anything related to vhdl 2008.
I already know that I need to set the file type to VHDL 2008. However, Vivado does not seem to pack that information into the IP block.
Could you please be more specific, if you know a way that works?
03-12-2015 10:40 AM - edited 03-12-2015 07:03 PM
Here is a snapshot to set VHDL 2008 in IP packaging window:
03-16-2015 04:53 AM
I tried setting the file types to "vhdlSource[space]2008". In other words, "vhdlSource", followed by space and the four-digit number 2008. Then I re-packaged the IP block, regenerated and tried to synthesize the project using that IP block.
Synthesis failed with the error message
[Synth-8-2757] this construct is only supported in VHDL 1076-2008
Either I misinterpreted your screen capture, and the keyword should have been something else. The tooltip only mentions vhdlSource-87, vhdlSource-93 and vhdlSource but is not explicit about how to declare vhdl 2008.
Was there a space bar or something else between vhdlSource and 2008? Did you do some other tricks, to allow a project to synthesize vhdl 2008-conforming ip blocks?
03-18-2015 07:14 PM
03-19-2015 01:34 AM
Thanks for the reply.
I can copy that: VHDL 2008 in that field indeed does change to vhdlSource 2008.
The information also seems to propagate to component.xml file in the IP directory.
After that, I repackaged that IP. Then, in the project, I tried upgrading IP, reinstantiating the IP, re-doing the output products, bd wrappers, etc.
Despite all these, synthesis fails if there are any actual VHDL-2008 constructs in use in the source file.
If I would, in addition to all the above, also apply the tricks of AR#62005 to the main project, then synthesis would fail due to error in ipif_pkg.vhd (which uses an identifier which was available in older VHDL but reserved in vhdl-2008. Consequently, declaring the entire project to be VHDL2008 is not an option as some of Xilinx's library files are not compatible with VHDL-2008.
How to proceed?
03-19-2015 01:58 AM
> If I would, in addition to all the above, also apply the tricks of AR#62005 to the main project, then synthesis would fail due to error in ipif_pkg.vhd
Manually fixing that by changing all the problematic names to something else, and working through a number of other files with similar symptoms allows me to synthesize.
This is not really a solution, as going through all those are generated files is a lot of work and the manual edists do not persist. In case of encrypted IP, that is not even possible. Maybe somebody at Xilinx should go through the vhd libraries, discontinue the use of "default" as an identifier? This would enhance the VHDL-2008 friendliness of the next Vivado release a lot.
In the meanwhile, how can I make Vivado synthesize my VHDL-2008 (and only that) in VHDL-2008 mode?
03-23-2015 08:43 AM
I would suggest you to post your last query on Synthesis board to target the correct audience.
07-07-2015 01:56 PM
I am also having problems with using VHDL 2008. I have used both the solution #2 of AR#52005 and setting the type of the files to either "VHDL 2008" (without quotes) or "vhdlSource 2008" (without quotes). In most higher level designs I am still getting errors about 2008 constructs even after updating the IP and after deleting blocks and replacing them back again.
07-07-2015 10:54 PM
Check these, this should solve your problem