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Newbie
Newbie
5,536 Views
Registered: ‎10-15-2011

VHDL incomplete port maps

Hey guys,

 

In my design process I decided to create a generic component with 3 vector inputs and 3 vector outputs that can do the same operation in paralel.

 

My problem is that some times I only need 1 of those inputs/outputs and I am not very sure how to implement that.

Can I use the original component and map just the inputs/outputs that are of interest for me?

 

generic component

 

component generic_component
	port (
	 in_a : in std_logic_vector(32 downto 0);
	 out_a : out std_logic_vector(32 downto 0);
	 in_b : in std_logic_vector(32 downto 0);
	 out_b : out std_logic_vector(32 downto 0);
	 in_d : in std_logic_vector(32 downto 0);
	 out_d  : out std_logic_vector(32 downto 0);
	);
end component;

 normal port map

	GENERIC_MAP: generic_component port map (
 in_a => sign1,
out_a =>sign2,
in_b =>sign3,
out_b =>sign4,
in_d =>sign5,
out_d  =>sign6);

wished port map

GENERIC_MAP: generic_component port map (
in_a => sign1,
out_a =>sign2);

 

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2 Replies
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Explorer
Explorer
5,520 Views
Registered: ‎07-24-2011

Yes you can do that with named port mapping. You can also use the keyword "open".

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Teacher
Teacher
5,504 Views
Registered: ‎09-09-2010

Also, you may find it helpful to give default values to the input ports.

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"If it don't work in simulation, it won't work on the board."
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