06-21-2016 01:59 AM - edited 06-21-2016 02:05 AM
Maybe a basic question about VHDL, but I read some comments against using 'alias' in VHDL, so :
When designing a custom AXI4-Lite IP using the templates generated by the 'create new IP wizard', I prefer to 'alias' some of the axi signals as follows :
alias clock is S_AXI_ACLK; alias reset_n is S_AXI_ARESETN;
From there on, I can just use 'clock' and 'reset' in any process sensitivity list, rising_edge(clock), and so on ... much more readable than S_AXI_ACLK.
If I would just rename S_AXI_ACLK to 'clock', the IP packager wouldn't recognize the group of AXI signals anymore as an AXI bus. Same for the reset signal.
Question : is there any disadvantage on using aliases in this way (synthesis & simulation wise)?
also at the same time a create a 'positive' reset signal for use in my vhdl code :
... signal reset : std_logic; begin reset <= not reset_n; ...
In my Zynq (IPI) design, the S_AXI_RESETN signal of the custom IP comes from a Processor System Reset block (peripheral_aresetn output).
Question : to have this positive reset available in the custom IP, would it be better to add an extra input to the IP, and use the positive reset output 'peripheral_reset' directly from the Processor System Reset block, instead of adding the inverter in my custom IP? (besides maybe wasting the inverter, but I find that neglectable).
06-22-2016 08:20 AM
06-23-2016 12:23 AM - edited 06-23-2016 12:26 AM
I tried the alias, and it is supported.
using assignment sounds indeed obvious, however when you do this with a clock, you can run into the most strangest simulation results, as the assignment adds a (simulation) delta-delay to the clock on the left side of the assignment, which results in 2 different simulated clocks.
You can see an example of that in another post of me here. It's due the way simulators work. Note that in the synthesized design this will most likely work, while it doesn't work in the simulation ... I learned from this issue that it is extremely important to understand how a simulator actually handles concurrency with delta delays.
For a regular signal the assignment is probably less of a problem in a synchronous design (?).
so the above issue is why I switched to using 'alias' instead of assignment. But I'm wondering if there is any other negative effect of doing so.
thanks for the tip on the interface naming - didn't try that : so I must manually add the 'renamed' axi clock signal to the axi interface?
09-16-2016 02:46 AM