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Registered: ‎10-10-2014

VHDL : is it ok to 'alias' S_AXI_ACLK and S_AXI_ARESETN inside a custom IP?

Maybe a basic question about VHDL, but I read some comments against using 'alias' in VHDL, so :


When designing a custom AXI4-Lite IP using the templates generated by the 'create new IP wizard', I prefer to 'alias' some of the axi signals as follows :


alias clock is S_AXI_ACLK;
alias reset_n is S_AXI_ARESETN;


From there on, I can just use 'clock' and 'reset' in any process sensitivity list, rising_edge(clock), and so on ... much more readable than S_AXI_ACLK.


If I would just rename S_AXI_ACLK to 'clock', the IP packager wouldn't recognize the group of AXI signals anymore as an AXI bus. Same for the reset signal.


Question : is there any disadvantage on using aliases in this way (synthesis & simulation wise)? 


also at the same time a create a 'positive' reset signal for use in my vhdl code :


signal reset : std_logic;

    reset <= not reset_n;


In my Zynq (IPI) design, the S_AXI_RESETN signal of the custom IP comes from a Processor System Reset block (peripheral_aresetn output). 


Question : to have this positive reset available in the custom IP, would it be better to add an extra input to the IP, and use the positive reset output 'peripheral_reset' directly from the Processor System Reset block, instead of adding the inverter in my custom IP? (besides maybe wasting the inverter, but I find that neglectable).

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Registered: ‎03-31-2012

* I am not sure if alias is supported by Vivado synthesis. I think you can easily declare another signal and assign to it instead of alias. The basic idea of renaming a signal is OK.

* I think BD automation is smart enough to connect axi_reset to peripheral_reset so it should be OK to do this. But not as an extra input (in addition to axi_reset_n) but instead.

One suggestion is that you really don't have to name your interfaces this way. You can always create them (semi-)manually if IP packager doesn't detect them. Actually you can rename them in any way you want and make them into interfaces in packager.
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Registered: ‎10-10-2014

Hello @muzaffer


I tried the alias, and it is supported. 


using assignment sounds indeed obvious, however when you do this with a clock, you can run into the most strangest simulation results, as the assignment adds a (simulation) delta-delay to the clock on the left side of the assignment, which results in 2 different simulated clocks.


You can see an example of that in another post of me here. It's due the way simulators work. Note that in the synthesized design this will most likely work, while it doesn't work in the simulation ... I learned from this issue that it is extremely important to understand how a simulator actually handles concurrency with delta delays.


For a regular signal the assignment is probably less of a problem in a synchronous design (?).


so the above issue is why I switched to using 'alias' instead of assignment. But I'm wondering if there is any other negative effect of doing so.


thanks for the tip on the interface naming - didn't try that : so I must manually add the 'renamed' axi clock signal to the axi interface? 



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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

In VIvado

First you need to generate the init.tcl file which is executed when starting Vivado. The TCL initialization script init.tcl file can be stored at two different locations:
1. In the software installation: <installdir>/Vivado/version/scripts/init.tcl
2. In the local user directory:
For Windows 7: %APPDATA%/Roaming/Xilinx/Vivado/init.tcl
For Linux: $HOME/.Xilinx/Vivado/init.tcl
An example for an init.tcl script including alias commands is shown below.

# My personal setup for vivado
interp alias {} h {} history
interp alias {} rts {} report_timing_summary
interp alias {} rtp {} report_timing -path_type full_clock_expanded -input_pins -nets
interp alias {} so {} select_objects
history keep 100


check this link as well
Thanks and Regards
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