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Adventurer
Adventurer
9,225 Views
Registered: ‎01-15-2013

VHO file not generating in PlanAhead

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Hello,

 

I am having a problem in Clocking Wizard of PlanAhead 14.4 and 14.6. I configured clocking wizard from IP catalog of PlanAhead. But planAhead fails to generate the .vho file and the hence I cannot  instantiate the IP cores. However, I could see the name of the core in a .xci file in design sources of the planAhead project.  The files are not generated in the project directory either. 

 

I don't have this problem if I instatniate another IP as I successully tested block RAM. I was wondering the reason for the failure to generate these files. 

 

regards,

Paul

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Xilinx Employee
Xilinx Employee
14,017 Views
Registered: ‎09-20-2012
Hi,

Right click on the IP ?xci file and choose "generate output products".

In "manage output products" window set the action for all files to "generate" and click on ok.

Check if this helps.

Thanks,
Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
14,018 Views
Registered: ‎09-20-2012
Hi,

Right click on the IP ?xci file and choose "generate output products".

In "manage output products" window set the action for all files to "generate" and click on ok.

Check if this helps.

Thanks,
Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Xilinx Employee
Xilinx Employee
9,213 Views
Registered: ‎07-11-2011

Hi,

 

I checked in 14.7.

It seems your observation is correct, BRAM is generating .vho by default but for clocking wizard you have to manually right click on .xci -> Generate output products -> Select instantiation template then only you can see .vho

 

But for simulation and syntheiss output products the behaviour looks similar

 

Should file a CR to have the compatibility meanwhile please use the genarate output products workaround.

 

 

Regards,

Vanitha.

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Xilinx Employee
Xilinx Employee
9,201 Views
Registered: ‎07-11-2011

Hi,

 

Additionally this issue is seen only in PlanAhead and Vivado is fine,  so better to go with the manual workaround and an AR as ISE/PlanAhead might not have new releases.

 

 

Hope this helps.

 

 

Regards,

Vanitha.

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Adventurer
Adventurer
9,186 Views
Registered: ‎01-15-2013
Thanks Vanitha and Deepika. Creating an answer record will be very helpful for the other users if XIlinx is not planning to release another version of ISE. I cannot migrate to Vivado as I am using Virtex 6 FPGA.
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