01-14-2019 03:40 AM
I have a fairly large design, implemented in system Verilog mostly. It synthesizes successfully but when I am trying to package it as IP the whole VIVADO crashes . This happens when Iam trying to merge changes in file group wizard or customization parameters wizard. I get a error report , attached here.
Any idea what is to reason for this problem?
Regards , Sirpa
01-14-2019 05:25 AM
01-16-2019 04:43 AM
like mentioned in my previous comment my OS is Centos 7.6.
looking at the list you gave only 7.2, 7.3 and 7.4 are supported. Usually version are backwards compatible but does this still mean that I have wrong OS version?
01-16-2019 08:52 PM
1. Check your design with supported CentOS version if it is installed in your colleague's machine. Else you may need to use supported CentOS on your machine.
2. What's the top level of your design? Is it a system verilog file?
01-17-2019 12:42 AM
Hi hemangd ,
1.I'll check my possibilities to try one of the supported OS versions, It is not very straightforward because we decided to use this Centos 7.6 and it is now installed to all of us.
2. Would Vivado 2018.3 make any difference?
3. It is system verilog design, toplevel and most of the other levels also.
01-17-2019 05:34 AM
Make sure the wrapper file is verilog only and not system verilog.
And Vivado 2018.3 supports till CentOS 7.5.
01-18-2019 03:49 AM
I manged to move to Centos 7.4. Vivado 2018.3 I have not yet tried.
But when opening the design in Centos 7.4 environment I got message "invalid top module..." please see the file attached. which of the three options I should choose?
01-21-2019 12:42 AM
1. Specify a new top module by navigating its path.
2. And also check what critical warnings are shown in the sources window.Resolve it, Because this could be the reason that vivado is not taking top module automatically. (As i can see 2 critical warnings in your last snapshot.)