04-06-2018 12:21 PM
Hi , I am starting working with VIVADO , coming from ISE , and I have a custom block in my block diagram with a AXI interface and inside this block , I edited the VHD and inserted my vhd components, it detects , I update the IP , and when I go back to generate my bitstream gives the error :
[DRC INBB-3] Black Box Instances: Cell 'design_1_i/axis_fifo_main_spn_0/U0/fifo_comp' of type 'design_1_axis_fifo_main_spn_0_0_fifoRam2' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
I tried to add it over and over , in the source or library , copying to the directory and all has failed .
04-06-2018 03:13 PM
Maybe UG1118 User Guide - Creating and Packaging Custom IP will help:
04-09-2018 08:50 AM
Please check this Answer Record https://www.xilinx.com/support/answers/61294.html, as it lists a few possible worksrounds to this issue. Hope this helps.