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Contributor
Contributor
669 Views
Registered: ‎04-06-2018

VIVADO not adding vhd file : black box instances

Hi , I am starting working with VIVADO , coming from ISE , and I have a custom block in my block diagram with a AXI interface and inside this block , I edited the VHD and inserted my vhd components, it detects , I update the IP , and when I go back to generate my bitstream gives the error :

 

[DRC INBB-3] Black Box Instances: Cell 'design_1_i/axis_fifo_main_spn_0/U0/fifo_comp' of type 'design_1_axis_fifo_main_spn_0_0_fifoRam2' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

 

I tried to add it over and over , in the source or library , copying to the directory and all has failed .

 

 

Screenshot from 2018-04-06 13-12-32.png
Screenshot from 2018-04-06 13-12-23.png
Screenshot from 2018-04-06 12-25-23.png
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2 Replies
Voyager
Voyager
646 Views
Registered: ‎03-28-2016

Re: VIVADO not adding vhd file : black box instances

Maybe UG1118 User Guide - Creating and Packaging Custom IP will help:

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Moderator
Moderator
590 Views
Registered: ‎06-14-2010

Re: VIVADO not adding vhd file : black box instances

Hello @maikonnascimento,

 

Please check this Answer Record https://www.xilinx.com/support/answers/61294.html, as it lists a few possible worksrounds to this issue. Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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