Can anybody help me to fix this issue on Verilog and Schematic? I keep getting this warning that is not letting me give me my simulation,
WARNING:Xst:737 - Found 1-bit latch for signal <D<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <D<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Here is my code:
module rom_content(A,D);
input [5:0] A; //This is the ROM Size
output [7:0] D;
reg [7:0] D;
always @ (A)
begin
if ( A == 6'h00) begin // State 0
D = 8'h00; //ROW 0
end
else if ( A == 6'h01) begin // State 0
D = 8'h00; //ROW 1
end
else if ( A == 6'h02) begin // State 0
D = 8'h10; //ROW 2
end
else if ( A == 6'h03) begin // State 0
D = 8'h10; //ROW 3
end
else if ( A == 6'h04) begin //State 1
D = 8'h2A; //ROW 4
end
else if ( A == 6'h05) begin // State 1
D = 8'h2A; //ROW 5
end
else if ( A == 6'h06) begin // State 1
D = 8'h2A; //ROW 6
end
else if ( A == 6'h07) begin // State 1
D = 8'h2A; //ROW 7
end
else if ( A == 6'h08) begin // State 2
D = 8'h32; //ROW 8
end
else if ( A == 6'h09) begin // State 2
D = 8'h32; //ROW 9
end
else if ( A == 6'h0A) begin // State 2
D = 8'h32; //ROW 10
end
else if ( A == 6'h0B) begin // State 2
D = 8'h32; //ROW 11
end
else if ( A == 6'h0C) begin // State 3
D = 8'h4A; //ROW 12
end
else if ( A == 6'h0D) begin // State 3
D = 8'h4A; //ROW 13
end
else if ( A == 6'h0E) begin // State 3
D = 8'h4A; //ROW 14
end
else if ( A == 6'h0F) begin // State 3
D = 8'h4A; //ROW 15
end
else if ( A == 6'h10) begin // State 4
D = 8'h52;
end
else if ( A == 6'h11) begin // State 4
D = 8'h52;
end
else if ( A == 6'h12) begin // State 4
D = 8'h52;
end
else if ( A == 6'h13) begin // State 4
D = 8'h52;
end
else if ( A == 6'h14) begin // State 5
D = 8'h6A;
end
else if ( A == 6'h15) begin // State 5
D = 8'h6A;
end
else if ( A == 6'h16) begin // State 5
D = 8'h6A;
end
else if ( A == 6'h17) begin // State 5
D = 8'h6A;
end
else if ( A == 6'h18) begin // State 6
D = 8'h7A;
end
else if ( A == 6'h19) begin // State 6
D = 8'h7A;
end
else if ( A == 6'h1A) begin // State 6
D = 8'h7A;
end
else if ( A == 6'h1B) begin // State 6
D = 8'h7A;
end
else if ( A == 6'h1C) begin // State 7
D = 8'h86;
end
else if ( A == 6'h1D) begin // State 7
D = 8'h86;
end
else if ( A == 6'h1E) begin // State 7
D = 8'h86;
end
else if ( A == 6'h1F) begin // State 7
D = 8'h86;
end
else if ( A == 6'h20) begin // State 8
D = 8'h85;
end
else if ( A == 6'h21) begin // State 8
D = 8'h95;
end
else if ( A == 6'h22) begin // State 8
D = 8'h85;
end
else if ( A == 6'h23) begin // State 8
D = 8'h95;
end
else if ( A == 6'h24) begin // State 9
D = 8'hA4;
end
else if ( A == 6'h25) begin // State 9
D = 8'hA4;
end
else if ( A == 6'h26) begin // State 9
D = 8'hA4;
end
else if ( A == 6'h27) begin // State 9
D = 8'hA4;
end
else if ( A == 6'h28) begin // State A
D = 8'hB2;
end
else if ( A == 6'h29) begin // State A
D = 8'hB2;
end
else if ( A == 6'h2A) begin // State A
D = 8'hB2;
end
else if ( A == 6'h2B) begin // State A
D = 8'hB2;
end
else if ( A == 6'h2C) begin // State B
D = 8'hC4;
end
else if ( A == 6'h2D) begin // State B
D = 8'hC4;
end
else if ( A == 6'h2E) begin // State B
D = 8'hC4;
end
else if ( A == 6'h2F) begin // State B
D = 8'hC4;
end
else if ( A == 6'h30) begin // State C
D = 8'h02;
end
else if ( A == 6'h31) begin // State C
D = 8'h02;
end
else if ( A == 6'h32) begin // State C
D = 8'h02;
end
else if ( A == 6'h33) begin // State C
D = 8'h02;
end
else if ( A == 6'h34) begin // State D
D = 8'h06;
end
else if ( A == 6'h35) begin // State D
D = 8'h06;
end
else if ( A == 6'h36) begin // State D
D = 8'h06;
end
else if ( A == 6'h37) begin // State D
D = 8'h06;
end
else if ( A == 6'h38) begin // State E
D = 8'h06;
end
else if ( A == 6'h39) begin // State E
D = 8'h06;
end
else if ( A == 6'h3A) begin // State E
D = 8'h06;
end
else if ( A == 6'h3B) begin // State E
D = 8'h06;
end
else if ( A == 6'h3C) begin // State F
D = 8'h06;
end
else if ( A == 6'h3D) begin // State F
D = 8'h06;
end
else if ( A == 6'h3E) begin // State F
D = 8'h06;
end
else if ( A == 6'h3F) begin // State F
D = 8'h06;
end
end // always ends
endmodule
Thank you in advance!!!
