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kopparthiv
Newbie
Newbie
1,079 Views
Registered: ‎02-09-2020

Verilog HDL based custom IP for the AXI-slave lite & BRAM interface

When HLS based IP generated for the AXI-slave lite & BRAM interface, then the BRAM port is connected to the BRAM automatically by Run Connection Automation in Vivado Block design. Required memory size information is updated into the Bram.

Problem:

When it comes to Verilog HDL based custom IP for the AXI-slave lite & BRAM interface, BRAM port in Custom IP is not connecting to the BRAM automatically in Vivado Block design. Required memory size information is updated into the Bram.

(* CORE_GENERATION_INFO = "Adddesign,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Adddesign,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Adddesign.hwdef" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA_0, MASTER_TYPE BRAM_CTRL, MEM_ECC NONE, MEM_SIZE 8192, MEM_WIDTH 32, READ_LATENCY 1" *) input [31:0]BRAM_PORTA_0_addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 CLK" *) input BRAM_PORTA_0_clk;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 DIN" *) input [31:0]BRAM_PORTA_0_din;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 DOUT" *) output [31:0]BRAM_PORTA_0_dout;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 EN" *) input BRAM_PORTA_0_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 RST" *) input BRAM_PORTA_0_rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA_0 WE" *) input [3:0]BRAM_PORTA_0_we;

How to group all the BRam ports variables in custom IP? What is the syntax for that?

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2 Replies
cdunlap
Xilinx Employee
Xilinx Employee
963 Views
Registered: ‎10-01-2007

You need to add the same interface in your custom IP.  You need to follow the same naming convention and you can use attributes to help force it.  The language templates has guidelines on how to do it.

language templates -> verilog -> Ip Integrator HDL -> advanced interfaces -> block ram inteface

That has an example of the attributes and the way to do the mapping.  Of course the X_interface_info should match to the same IP you are using and you can see which one is being used in the IP xml file.

ronnywebers
Advisor
Advisor
907 Views
Registered: ‎10-10-2014

@cdunlap I'm struggling with a very closely related question, would you mind taking a look at my forum post :

"how to add a (dual port) BRAM inside a custom IP and expose one port as a BRAM interface on the IP"

thanks in advance!

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