cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
7,295 Views
Registered: ‎09-09-2009

Verilog coding...

Jump to solution

I am trying to implement some logic in ISE for ML507.

I have an if statement as follows:

reg [285:0] pcbank_df_obuff;
reg [15:0] data_threshold;
integer pcbank_df_obuff_pos;
.
.
.
always @(posedge clk0) begin
if(reset) begin
.
.
pc_af_obuff <= 0;
pc_af_obuff_pos <= 0;
.
.
.
end else begin
.
.
.
pc_df_obuff <= pc_df_out;
pc_df_obuff_pos <= 224;
..
.
.
  if(pcbank_df_obuff[(pcbank_df_obuff_pos+15) : pcbank_df_obuff_pos] > data_threshold[15:0]) begin

    pc_df_ibuff[15:0] <= pcbank_df_obuff[pcbank_df_obuff_pos + 15 : pcbank_df_obuff_pos];
    zero_datapts_cnt <= 0;
  end else begin
    pc_df_ibuff[15:0] <= 16'b0; // writes 16'b0 to out data fifo
    zero_datapts_cnt <= zero_datapts_cnt + 1;// increments seq zero datapoint cntr
   end
 end
end

 

I am getting following errors:
ERROR:HDLCompilers:109 - "adder_src/data_compressor.v" line 511 Most significant bit operand in part-select of vector reg 'pcbank_df_obuff' is illegal
ERROR:HDLCompilers:110 - "adder_src/data_compressor.v" line 511 Least significant bit operand in part-select of vector reg 'pcbank_df_obuff' is illegal
ERROR:HDLCompilers:71 - "adder_src/data_compressor.v" line 511 Illegal condition expression in if statement
ERROR:HDLCompilers:109 - "adder_src/data_compressor.v" line 512 Most significant bit operand in part-select of vector reg 'pcbank_df_obuff' is illegal
ERROR:HDLCompilers:110 - "adder_src/data_compressor.v" line 512 Least significant bit operand in part-select of vector reg 'pcbank_df_obuff' is illegal
ERROR:HDLCompilers:107 - "adder_src/data_compressor.v" line 512 Illegal right hand side of nonblocking assignment

Is there a way to implement this kind of if loops? Can you guys help me please with this issue?

 

 

Thanks,

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Professor
Professor
9,714 Views
Registered: ‎08-14-2007

Verilog synthesis does not allow arbitrary upper and lower range selects.  Either

both upper and lower range must evaluate to a constant like foo[8-5:1] or you

can have only a single variable like foo[loop+3], or you can have a single variable

with a width specifier like foo[loop +:8]

 

Width specifiers allow you to select either the MSB or the LSB of the range and

then specify the number of bits.  The foo[loop +:8] syntax means select 8 bits

starting from "loop" at the LSB and going up from there.  It is equivalent to

the illegal syntax foo[(loop+7) : loop]

 

Similarly the -: operator allows you to specify the MSB and work down so

foo[loop -:8] is equivalent to foo[loop : (loop - 7)]

 

HTH,

Gabor

-- Gabor

View solution in original post

3 Replies
Highlighted
Professor
Professor
9,715 Views
Registered: ‎08-14-2007

Verilog synthesis does not allow arbitrary upper and lower range selects.  Either

both upper and lower range must evaluate to a constant like foo[8-5:1] or you

can have only a single variable like foo[loop+3], or you can have a single variable

with a width specifier like foo[loop +:8]

 

Width specifiers allow you to select either the MSB or the LSB of the range and

then specify the number of bits.  The foo[loop +:8] syntax means select 8 bits

starting from "loop" at the LSB and going up from there.  It is equivalent to

the illegal syntax foo[(loop+7) : loop]

 

Similarly the -: operator allows you to specify the MSB and work down so

foo[loop -:8] is equivalent to foo[loop : (loop - 7)]

 

HTH,

Gabor

-- Gabor

View solution in original post

Highlighted
Visitor
Visitor
7,253 Views
Registered: ‎09-09-2009

That helped!

 

Thanks,

Bhuvan

0 Kudos
Highlighted
Anonymous
Not applicable
2,906 Views

using a loop on i  got that error for

     

data[i+:3]

   

its seems that that solution did not work my workaround is :

      

data[i] <= data_in[0];      
data[i+1] <= data_in[1];
data[i+2] <= data_in[2];
data[i+3] <= data_in[3];

 

0 Kudos