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Observer stu2k@msn.com
Registered: ‎11-22-2014

Verilog library and/or custom IP management

As I have been working on various Verilog projects I have essentially created a library of various module including all sorts of flip flops, counters, muxes, etc.  As I actually make the project (usually in the text editor, not with block diagrams) I tend to copy and paste parts of my library into my new project so I can use those old components.  Once I have that project completed I package it as IP so I can use it in the block diagram for my Zynq solution on my Zedboard.  This doesn't seem like it is the best solution to manage my library of components.


The answer to this is probably very subjective, but what is the best way to manages Verilog libraries?  Is it best to just package each component as custom IP and use block diagrams with the IP Report tool?  Package a directory (not that I have tried that yet)?  If block diagrams is the answer, how can your top level Counter module which defines a counter (register) width reach down to the underlying flip flops and resize to the appropriate width?  That is easy in a text file, I've never found out how to do that in a block diagram.


I have thought about having a series of files like FlipFlops.v (which would be included in Counters.v), muxes.v and then just adding the associated file to the project.  Breaking FlipFlops.v into Dff.v and DffWithClockEnable.v and so on seems like it would get too cumbersome.

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