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whisper
Visitor
Visitor
7,863 Views
Registered: ‎04-07-2014

Verilog question about Illegal redeclaration of OUTPUT

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未命名.PNG

I am beginner
And I really want to know why it was error
If I don't declare reg [7:0] M; the always@() block can't be used, right ?
I am confused and do not know how to correct

What should I do?

 

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1 Solution

Accepted Solutions
hj
Moderator
Moderator
11,869 Views
Registered: ‎06-05-2013
Please right it as
module pipeline_multiplier(
input [3:0] A,B,
input clk,
output reg [7:0] M);
Please change it & comment 28 line.

Regards,
Harry
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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4 Replies
hj
Moderator
Moderator
11,870 Views
Registered: ‎06-05-2013
Please right it as
module pipeline_multiplier(
input [3:0] A,B,
input clk,
output reg [7:0] M);
Please change it & comment 28 line.

Regards,
Harry
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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whisper
Visitor
Visitor
7,843 Views
Registered: ‎04-07-2014

Thank you very much

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hj
Moderator
Moderator
7,839 Views
Registered: ‎06-05-2013
Could you please add the code as a text file so that we can try at our end also. Ideally which you have declared is also correct. Tool should not throw error as what you have declared is verilog 95 syntax. I have tried to synthesize the same code but I am not getting the error. Below is the code:

module pipeline_multiplier( input [3:0] A,B,
input clk,
output [7:0] M
);

reg [7:0] tmp1,tmp2,tmp3,tmp4,tmp12,tmp34;
reg state=0;
reg [7:0] M;

always @ (posedge clk)
case (state)
0: begin
if (B[0])
tmp1 = {A[3],A[3],A[3],A[3],A};
else
tmp1 =0;
if (B[1])

tmp2 = {A[3],A[3],A[3],A,1'b0};
else
tmp2 =0;

if (B[2])
tmp3 = {A[3],A[3],A,2'b00};
else
tmp3 =0;
if (B[3])
tmp4 = {A[3],A,3'b000};
else
tmp4 =0;

end
1: begin
M= tmp1+tmp2+tmp3+tmp4;
state =0;
end
endcase

endmodule

Please use latest ISE 14.7 as there is lot of bug which has been fixed.

Regards,
Harry


-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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whisper
Visitor
Visitor
7,833 Views
Registered: ‎04-07-2014

I have try some method and I think because I was used ISE 10.1

So I need declared like

----------------------------------------------------------------

module pipeline_multiplier( input [3:0] A,B,
input clk,
output reg[7:0] M
);

reg [7:0] tmp1,tmp2,tmp3,tmp4,tmp12,tmp34;
reg state=0;

-----------------------------------------------------------------

or

----------------------------------------------------------------

module pipeline_multiplier(A,B,clk,M);

input [3:0] A,B;

input clk;
output reg[7:0] M;

reg [7:0] tmp1,tmp2,tmp3,tmp4,tmp12,tmp34;
reg state=0;

-----------------------------------------------------------------

And now it was correct

I thank you very much for helping me to think so carefully