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Verilog wrapper for system verilog interface with inout ports

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Posts: 30
Registered: ‎03-17-2017

Verilog wrapper for system verilog interface with inout ports

I've been utilizing the system verilog interface feature to simplify and organize my code better. Unfortunately though, when packaging IP with Vivado you need to use a verilog wrapper. In order to accommodate my interfaces I've resorted to writing an interface converter that sits between my verilog wrapper and system verilog top design file...

 

verilog_wrapper.v (top module for the purpose of packaging IP)

system_verilog_interface_converter.sv (declares interfaces and then breaks out their signals to individual ports)

system_verilog_top.sv (actual top of my design, WISH I could just package from this)

design_modules.sv (multiple design files that all use interfaces)

 

...Until now I've never had to deal with an interface that includes an inout port. I've begun using the MIG IP which generates a DDR4 interface that includes inout ports for signals like the "dq" that are truly bi-directional. The question is how does one perform an interface conversion of an inout port? It can't just be assigned as a normal input or output signal would be as this would indicate a one way directionality.

 

Here is a sampling of what the interface looks like...

interface intf_ddr4 #(
	// Width of Address Bus (18 - 17)
	parameter ADDR_WIDTH = 17,
	// Width of DQ Bus (min 8, mult of 8)
	parameter DQ_WIDTH = 64
);

  logic [ADDR_WIDTH-1:0] adr;
  logic [DQ_WIDTH-1:0] dq;

modport std (
    output adr,
    inout  dq);

endinterface

 The interface converter would look something like this...

module intf_converter (
  //DDR4 interface
  output [16:0] ddr4_adr,
  inout [63:0] ddr4_dq
);

//interface declerations
intf_ddr4 ddr4();

//interface mapping
assign ddr4_adr = ddr4.adr;
assign ddr4_dq??? 

//system verilog top module
sv_top sv_top (
  .ddr4 (ddr4));

...so you can see the dilemma, but I'm hoping someone has a neat solution to this issue