08-17-2016 04:48 AM
I am using Viterbi Decoder v9.0 in my design with a Zync 7010 with Vivado 2015.4
Transfer of Data should be
done by AX_DMA, However there is a critical warning:
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
Can it be ignored??
I have not found any example design for viterbi. Maybe DMA is not the mechanism for data transfer to/from viterbi.
Is there a recent design example available? Unfortunetely There is none on the XIlinx WIKI.
08-17-2016 06:15 AM
It looks like the AXI Direct Memory Access S_AXIS_S2MM port does have the tlast signal in it ( see attached image ), and the Viterbi Decoder ( 9.1 ) does not have tlast in its M_AXIS_DATA port ( see attached image .
Per page 65 of the AXI Direct Memory Access datasheet:
The Current Descriptor and Tail Descriptor registers should be programmed before the packet/data arrives. AXI DMA holds the streaming data by deasserting tready until the corresponding descriptors are fetched. Then, AXI DMA writes start at the Buffer Address and continues until tlast is received from the streaming side. For a particular channel when the data transfer is completed, the current descriptor register will be loaded with the address of the next descriptor in that chain.
It does look like the DMA engine is looking for a tlast signal, however this may be to tell the engine to start the transfer prior to the maximum data packet size being reached.
It may be worth building the design and trying to get data moving in a bare-metal app without the tlast being asserted first, then moving to Linux.
08-17-2016 07:48 AM
08-18-2016 07:04 AM - edited 08-18-2016 07:04 AM
What is the Xilinx recommended way to transfer data from/to the Viterbi IP?
Well you can still connect Viterbi to the AXI DMA and use it successfully; you just have to provide tlast outside of the core. Generate it using a counter or something. This is exactly how those designs I showed you work.
In fact, you can use an AXI Stream Subset converter to automatically generate tlast for you at pre-defined number of sample intervals.
08-21-2016 02:24 AM
thank you for the hints.
As I have a variable bit size for VITERBI your proposal with a binary counter (clk connected to tvalid) plus utility logic to generate TLAST should work.
I will configure the counter as loadable to satisfy the need for variable bit size.