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Observer williamsf2
Observer
124 Views
Registered: ‎01-14-2015

Vivado 16.4 compile errors

Hi, Wondered anyone could help with a compile error I cant seem to clear.

Im using a 32bit register and slicing off bits 13 to 28, so bit 0 to 12 are not required. Problem is I keep getting an error saying bits 0 to 12 are unplaced?

Do I ned to tie them off or smthg else even though they are not used?

 

viv_v1.JPG

Here is the circuit with the sliced bits:-

viv_v2.JPG

Any help would eb most appreciated..

Thanks

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2 Replies
Xilinx Employee
Xilinx Employee
116 Views
Registered: ‎05-22-2018

Re: Vivado 16.4 compile errors

Hi @williamsf2 ,

Use the following tcl commands for OOC flow to resolve the issue,
 
synth_design -mode out_of_context
launch_simulation -mode "post-synthesis" -type "functional"
opt_design
place_design
route_design
launch_simulation -mode "post-implementation" -type "functional".
 
Also please check this post:
 
Thanks,
Raj
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Observer williamsf2
Observer
107 Views
Registered: ‎01-14-2015

Re: Vivado 16.4 compile errors

Hi, Mny thanks and I will try this.

Could you explain what each line does and why do I need to do this?

 

Thanks

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