UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
257 Views
Registered: ‎03-04-2018

[Vivado 18.2] File replacement bug treats .sv files as .v

Not sure this is the right subsection but I didn't see any better choice.

I'd like to report a tool bug. There is an option in the GUI to replace an existing verilog source file with a different file. When replacing a legacy verilog .v file with a SystemVerilog .sv file, it appears that the tool doesn't switch context to SystemVerilog. It parses the .sv file as .v and so you will get errors such as the tool not understanding what the "logic" type is.

2 Replies
Xilinx Employee
Xilinx Employee
198 Views
Registered: ‎05-22-2018

Re: [Vivado 18.2] File replacement bug treats .sv files as .v

Hi @silverace99work ,

I guess the Replace By switch only helps with replacing the files specific to one language.

For instance for verilog file, you can replace it by (.v,.vf,.verilog,.vr,.vg...etc):

addervwerilogCapture.JPG

While if you allow it for all files then you have to mannuly set the fileset.

Thanks,

Raj

0 Kudos
Contributor
Contributor
155 Views
Registered: ‎03-04-2018

Re: [Vivado 18.2] File replacement bug treats .sv files as .v

@rshekhaw yes that seems to be what it is doing, but the tool should be able to handle that. Instead it drops it on the floor which is why I'm suggesting that it is a bug.

0 Kudos