Vivado 2013.04, "IP Ports" list disappear every time running "Package Block Design"
I see an issue when running "Package Block Design" in Vivado to Package your Block Design.
You create a Block Design, and then go through the entire "Package Block Design" flow and make the packaged ip.
Now, if you run the "Package Block Design" again, you will see that all of the fields are the same as what you have set
during your previous run, but in "IP Ports" section, no port is listed and you should run "Port Import Diaglog" again.
Up to this point, it is not a problem but, now, if you import ports, and then go through the rest of the flow and change some thing else (e.g. I updated the "IP addressing and Memory") now if you come back to "IP Ports" you can see that again it is empty.
In fact, every time that I produce a Packaged Block Design IP, I do first the Port Import,
Then I do the IP addressing and Memory and I define the Memory Access Range of AXI Masters,
then I check the Port list again to make sure that there are there.
Now, if I don't do the above, when I instantiate the Packaged Block Design , inside another design,
I see that the block appears in its complete port list. (all of the AXI masters and slaves are there)
But Vivado does not consider this ports as an AXI Master or AXI slave port.
In this case, if I put an AXI interconnect and connect for example, the AXI master port of my design
to an AXI Slave, I see that in Vivado Address Editor, the connection is not seen and the
AXI slave block is under the "Unconnected Slaves" group. (which is very confusing if you don't know